The Experts below are selected from a list of 1053 Experts worldwide ranked by ideXlab platform
Bernard Blackham - One of the best experts on this subject based on the ideXlab platform.
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Title: Towards Verified Microkernels for Real-Time Mixed-Criticality Systems
2014Co-Authors: Bernard BlackhamAbstract:Abstract 350 words maximum: (PLEASE TYPE) Today's embedded systems are becoming increasingly complex. We are seeing many devices consolidate both mission-critical real-time subsystems with convenience functionality such as networking stacks and graphical user interfaces. For example, medical implants such as pacemakers now provide wireless monitoring and control; bugs within the wireless subsystem must not be able to affect the safetycritical real-time operations of the pacemaker. Traditionally, this is achieved by using multiple processors with limited communication channels. However, these extra processors add significant overheads of size, weight and power. The mixed-criticality design promises to mitigate these overheads by consolidating multiple subsystems onto a single CPU, but this entails both mission-critical and convenience functionality sharing the same processor. In order to enforce isolation between subsystems of differing criticalities, we require a trustworthy supervisor to mediate control over the processor and provide behavioural guarantees. In this thesis, we explore several ingredients required to construct a high-assurance mixed-criticality real-time system. We propose that the formal verification and design of the seL4 microkernel makes it highly suited as a trustworthy foundation for these systems. We show how to compute Interrupt response time guarantees which complement seL4's guarantees of functional correctness. We also explore the design space for such microkernels, which must balance the competing goals of formal verification and real-time responsiveness. We investigate the limits of Interrupt Latency for non-preemptible microkernels, and question whether fully-preemptible kernels are necessary for low-Interrupt Latency applications
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improving Interrupt response time in a verifiable protected microkernel
European Conference on Computer Systems, 2012Co-Authors: Bernard Blackham, Gernot HeiserAbstract:Many real-time operating systems (RTOSes) offer very small Interrupt latencies, in the order of tens or hundreds of cycles. They achieve this by making the RTOS kernel fully preemptible, permitting Interrupts at almost any point in execution except for some small critical sections. One drawback of this approach is that it is difficult to reason about or formally model the kernel's behavior for verification, especially when written in a low-level language such as C. An alternate model for an RTOS kernel is to permit Interrupts at specific preemption points only. This controls the possible interleavings and enables the use of techniques such as formal verification or model checking. Although this model cannot (yet) obtain the small Interrupt latencies achievable with a fully-preemptible kernel, it can still achieve worst-case latencies in the range of 10,000s to 100,000s of cycles. As modern embedded CPUs enter the 1 GHz range, such latencies become acceptable for more applications, particularly when they come with the additional benefit of simplicity and formal models. This is particularly attractive for protected multitasking microkernels, where the (inherently non-preemptible) kernel entry and exit costs dominate the latencies of many system calls. This paper explores how to reduce the worst-case Interrupt Latency in a (mostly) non-preemptible protected kernel, and still maintain the ability to apply formal methods for analysis. We use the formally-verified seL4 microkernel as a case study and demonstrate that it is possible to achieve reasonable response-time guarantees. By combining short predictable Interrupt latencies with formal verification, a design such as seL4's creates a compelling platform for building mixed-criticality real-time systems.
Michael J. Burke - One of the best experts on this subject based on the ideXlab platform.
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99PC-314 A Hybrid System Solution Of The Interrupt Latency Compatibility Problem
2009Co-Authors: Feng Lin, David T. Ashley, Michael Heymann, Michael J. BurkeAbstract:Microprocessors and microcontrollers are now widely used in automobiles. Microprocessor systems contain sources of Interrupt and Interrupt service routines, which are software components executed in response to the assertion of an Interrupt in hardware. A major problem in designing the software of microprocessor systems is the analytical treatment of Interrupt Latency. Because multiple Interrupt service routines are executed on the same CPU, they compete for the CPU and interfere with each other's Latency requirements. Here, Interrupt Latency is defined as the delay between the assertion of the Interrupt in hardware and the start of execution of the associated Interrupt service routine. It is estimated that 80 % of intermittent bugs in small microprocessor software loads are due to improper treatment of Interrupts. Until this work, there is no analytic method for analyzing a particular system to determine if it may violate Interrupt Latency requirements. There is also no reliable empirical method for ruling out the possibility of Interrupt Latency violations in a particular system, as they may occur under only very specific conditions. We use a newly developed hybrid system approach to solve this Interrupt Latency compatibility analysis problem. We have developed an efficient algorithm to determine if Interrupt Latency violations may occur in a particular system. A software tool that implements the algorithm is also being developed. With such software, we can easily check if Interrupt Latency constraints may be violated under any circumstances. If so, such software may also indicate how to modify the Interrupts and Interrupt service routines to avoid such violations
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A Hybrid System Solution Of The Interrupt Latency Compatibility Problem
2008Co-Authors: Feng Lin, David T. Ashley, Michael Heymann, Michael J. BurkeAbstract:Microprocessors and microcontrollers are now widely used in automobiles. Microprocessor systems contain sources of Interrupt and Interrupt service routines, which are software components executed in response to the assertion of an Interrupt in hardware. A major problem in designing the software of microprocessor systems is the analytical treatment of Interrupt Latency. Because multiple Interrupt service routines are executed on the same CPU, they compete for the CPU and interfere with each other's Latency requirements. Here, Interrupt Latency is defined as the delay between the assertion of the Interrupt in hardware and the start of execution of the associated Interrupt service routine. It is estimated that 80 % of intermittent bugs in small microprocessor software loads are due to improper treatment of Interrupts. Until this work, there is no analytic method for analyzing a particular system to determine if it may violate Interrupt Latency requirements. There is also no reliable empirical method for ruling out the possibility of Interrupt Latency violations in a particular system, as they may occur under only very specific conditions. We use a newly developed hybrid system approach to solve this Interrupt Latency compatibility analysis problem. We have developed an efficient algorithm to determine if Interrupt Latency violations may occur in a particular system. A software tool that implements the algorithm is also being developed. With such software, we can easily check if Interrupt Latency constraints may be violated under any circumstances. If so, such software may also indicate how to modify the Interrupts and Interrupt service routines to avoid such violations
Gernot Heiser - One of the best experts on this subject based on the ideXlab platform.
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improving Interrupt response time in a verifiable protected microkernel
European Conference on Computer Systems, 2012Co-Authors: Bernard Blackham, Gernot HeiserAbstract:Many real-time operating systems (RTOSes) offer very small Interrupt latencies, in the order of tens or hundreds of cycles. They achieve this by making the RTOS kernel fully preemptible, permitting Interrupts at almost any point in execution except for some small critical sections. One drawback of this approach is that it is difficult to reason about or formally model the kernel's behavior for verification, especially when written in a low-level language such as C. An alternate model for an RTOS kernel is to permit Interrupts at specific preemption points only. This controls the possible interleavings and enables the use of techniques such as formal verification or model checking. Although this model cannot (yet) obtain the small Interrupt latencies achievable with a fully-preemptible kernel, it can still achieve worst-case latencies in the range of 10,000s to 100,000s of cycles. As modern embedded CPUs enter the 1 GHz range, such latencies become acceptable for more applications, particularly when they come with the additional benefit of simplicity and formal models. This is particularly attractive for protected multitasking microkernels, where the (inherently non-preemptible) kernel entry and exit costs dominate the latencies of many system calls. This paper explores how to reduce the worst-case Interrupt Latency in a (mostly) non-preemptible protected kernel, and still maintain the ability to apply formal methods for analysis. We use the formally-verified seL4 microkernel as a case study and demonstrate that it is possible to achieve reasonable response-time guarantees. By combining short predictable Interrupt latencies with formal verification, a design such as seL4's creates a compelling platform for building mixed-criticality real-time systems.
Stamatis Vassiliadis - One of the best experts on this subject based on the ideXlab platform.
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A low-power multithreaded processor for software defined radio
Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, 2006Co-Authors: Michael Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Sanjay Jinturkar, Stamatis VassiliadisAbstract:Embedded digital signal processors for software defined radio have stringent design constraints including high computational bandwidth, low power consumption, and low Interrupt Latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for software defined radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for software defined radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in software on a variety of communication protocols including 802.11b, GPS, AM/FM radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.
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a low power multithreaded processor for baseband communication systems
International Conference Workshop on Embedded Computer Systems: Architectures Modeling and Simulation, 2004Co-Authors: Michael J. Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Stamatis VassiliadisAbstract:Embedded digital signal processors for baseband communication systems have stringent design constraints including high computational bandwidth, low power consumption, and low Interrupt Latency. Furthermore, these processors should be compiler-friendly, so that code for them can quickly be developed in a high-level language. This paper presents the design of a high-performance, low-power digital signal processor for baseband communication systems. The processor uses token triggered threading, SIMD vector processing, and powerful compound instructions to provide real-time baseband processing capabilities with very low power consumption. Using a super-computer class vectorizing compiler, the processor achieves real-time performance on a 2Mbps WCDMA transmission system.
Shao Z - One of the best experts on this subject based on the ideXlab platform.
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On improving real-time Interrupt latencies of hybrid operating systems with two-level hardware Interrupts
Institute of Electrical and Electronics Engineers, 2011Co-Authors: Liu M, Liu D, Wang Y, Wang M, Shao ZAbstract:In this paper, we propose to implement hybrid operating systems based on two-level hardware Interrupts. We analyze and model the worst-case real-time Interrupt Latency for RTAI and identify the key component for its optimization. Then, we propose our methodology to implement hybrid operating systems with two-level hardware Interrupts by combining the real-time kernel and the time-sharing OS (Operating System) kernel. Based on the methodology, we discuss the important issues for the implementation. Finally, we implement a hybrid system called RTLinux-THIN (Real-Time LINUX with Two-level Hardware Interrupts) on the ARM architecture by combining ARM Linux kernel 2.6.9 and murm C/OS-rm II}. We conduct experiments on a set of real application programs including mplayer, Bonnie, and iperf, and compare the Interrupt Latency and Interrupt task distributions for RTLinux-THIN (with and without cache locking), RTAI, Linux, and Linux with RT patch on a hardware platform based on Intel PXA270 processor. The results show that our scheme not only provides an easy method for implementing hybrid systems but also achieves the performance improvement for both the time-sharing and real-time subsystems.Department of Computin
