The Experts below are selected from a list of 450 Experts worldwide ranked by ideXlab platform
Winfried Kalfa - One of the best experts on this subject based on the ideXlab platform.
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Structuring Interrupts in
2007Co-Authors: Kernel Operating, Sven Graupner, Winfried KalfaAbstract:ion always causes costs. But limiting costs to a minimum can prove abstractions to be applicable. Our scheme of a process-oriented Interrupt handling scheme based on dedicated Interrupt processes called iproc's is more general and equally efficient compared to conventional handling Interrupts on the bare CPU. But there are semantical advantages which are cheaply to gain using iproc's. Interleaving of Interrupts is well suited to iproc's. There is just more than one iproc at any point in time representing each Interrupt. A policy decides which to run. Interleaving Interrupts of conventional schemes share the same Interrupt Stack to store state information of Interrupted ISR's. Using this dynamic Stack-organized memory allocation to store state information of Interrupted ISR's implies an procedural order of processing. There is a dependency between a memory allocation scheme and a processing order of ISR's that should be avoided. We cope with this dependency by providing each of our ipro..
Kernel Operating - One of the best experts on this subject based on the ideXlab platform.
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Structuring Interrupts in
2007Co-Authors: Kernel Operating, Sven Graupner, Winfried KalfaAbstract:ion always causes costs. But limiting costs to a minimum can prove abstractions to be applicable. Our scheme of a process-oriented Interrupt handling scheme based on dedicated Interrupt processes called iproc's is more general and equally efficient compared to conventional handling Interrupts on the bare CPU. But there are semantical advantages which are cheaply to gain using iproc's. Interleaving of Interrupts is well suited to iproc's. There is just more than one iproc at any point in time representing each Interrupt. A policy decides which to run. Interleaving Interrupts of conventional schemes share the same Interrupt Stack to store state information of Interrupted ISR's. Using this dynamic Stack-organized memory allocation to store state information of Interrupted ISR's implies an procedural order of processing. There is a dependency between a memory allocation scheme and a processing order of ISR's that should be avoided. We cope with this dependency by providing each of our ipro..
Sven Graupner - One of the best experts on this subject based on the ideXlab platform.
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Structuring Interrupts in
2007Co-Authors: Kernel Operating, Sven Graupner, Winfried KalfaAbstract:ion always causes costs. But limiting costs to a minimum can prove abstractions to be applicable. Our scheme of a process-oriented Interrupt handling scheme based on dedicated Interrupt processes called iproc's is more general and equally efficient compared to conventional handling Interrupts on the bare CPU. But there are semantical advantages which are cheaply to gain using iproc's. Interleaving of Interrupts is well suited to iproc's. There is just more than one iproc at any point in time representing each Interrupt. A policy decides which to run. Interleaving Interrupts of conventional schemes share the same Interrupt Stack to store state information of Interrupted ISR's. Using this dynamic Stack-organized memory allocation to store state information of Interrupted ISR's implies an procedural order of processing. There is a dependency between a memory allocation scheme and a processing order of ISR's that should be avoided. We cope with this dependency by providing each of our ipro..
Ali Gulbag - One of the best experts on this subject based on the ideXlab platform.
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bzk sau implementing a hardware and software based computer architecture simulator for educational purpose
International Conference on Computer Design, 2010Co-Authors: Halit Oztekin, Feyzullah Temurtas, Ali GulbagAbstract:The most ideal learning about a topic is to put the theoretical knowledge into practice. Computer Architecture and Organization course plays a significant role in the electronics engineering, computer engineering and similar disciplines. To convert practice the concepts handled in this course is not easy task. In this paper, we present a computer architecture simulator design named BZK.SAU. It has fifty-nine instructions that are commonly used in commercial microprocessors. Also, it has eleven registers and implements Interrupt, Stack and input-output operations. This simulator with memory of 64 KB uses sixteen bits data bus to communicate between registers, memory, and peripheral devices. This simulator is a useful tool for Computer Architecture and Organization course since all units of this simulator can be examined in detail. Many of the simulators in the literature have been designed using a software programming language. These simulators can help to enhance learning the concepts in Computer Architecture and Organization course. However, examining the internal structure of the units in these simulators is not possible. The simulator designed in this paper allows being able to analyze the internal structures since all units of this simulator was designed at logic gate level. Additionally, the Assembler and Compiler Programs was written for this Simulator in the Microsoft Visual Studio. NET platform. The students can watch the execution of the assembly code written using these programs. Also, they can watch step by step changes on its registers and other units by adjusting the clock speed in the simulator.
Halit Oztekin - One of the best experts on this subject based on the ideXlab platform.
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bzk sau implementing a hardware and software based computer architecture simulator for educational purpose
International Conference on Computer Design, 2010Co-Authors: Halit Oztekin, Feyzullah Temurtas, Ali GulbagAbstract:The most ideal learning about a topic is to put the theoretical knowledge into practice. Computer Architecture and Organization course plays a significant role in the electronics engineering, computer engineering and similar disciplines. To convert practice the concepts handled in this course is not easy task. In this paper, we present a computer architecture simulator design named BZK.SAU. It has fifty-nine instructions that are commonly used in commercial microprocessors. Also, it has eleven registers and implements Interrupt, Stack and input-output operations. This simulator with memory of 64 KB uses sixteen bits data bus to communicate between registers, memory, and peripheral devices. This simulator is a useful tool for Computer Architecture and Organization course since all units of this simulator can be examined in detail. Many of the simulators in the literature have been designed using a software programming language. These simulators can help to enhance learning the concepts in Computer Architecture and Organization course. However, examining the internal structure of the units in these simulators is not possible. The simulator designed in this paper allows being able to analyze the internal structures since all units of this simulator was designed at logic gate level. Additionally, the Assembler and Compiler Programs was written for this Simulator in the Microsoft Visual Studio. NET platform. The students can watch the execution of the assembly code written using these programs. Also, they can watch step by step changes on its registers and other units by adjusting the clock speed in the simulator.
