The Experts below are selected from a list of 495 Experts worldwide ranked by ideXlab platform
Todor Stefanov - One of the best experts on this subject based on the ideXlab platform.
-
System Design using kahn process networks: The Compaan/Laura Approach
2012Co-Authors: Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart KienhuisAbstract:New emerging embedded system platforms in the realm of highthroughput multimedia, imaging, and signal processing will consist of multiple microprocessors and reconfigurable components. One of the major problems is how to program these platforms in a systematic and automated way so as to satisfy the performance need of applications executed on these platforms. In this paper, we present our system design approach as an efficient solution to this programming problem. We show how for an application written in Matlab, a kahn process network specification can automatically be derived and systematically mapped onto a target platform composed of a microprocessor and an FPGA. Furthermore, we illustrate how the mapping approach is applied on a real-life example, namely an M-JPEG encoder. 1
-
On Compile-time Evaluation of process Partitioning Transformations for kahn process networks
2009Co-Authors: Sjoerd Meijer, See Profile, Hristo Nikolov, Todor StefanovAbstract:On compile-time evaluation of process partitioning transformations for kahn process network
-
Affine nested loop programs and their binary cyclo-static dataflow counterparts
2006Co-Authors: F. Deprettere, Todor Stefanov, Shuvra S. Bhattacharyya, Mainak SenAbstract:Parameterized static affine nested loop programs can be automatically converted to input-output equivalent kahn process network specifications. These networks turn out to be close relatives of parameterized cyclo-static dataflow graphs. Token production and consumption can be cyclic with a finite number of cycles or finite non-cyclic. More-over the token production and consumption se-quences are binary. 1
-
system design using kahn process networks the compaan laura approach
Design Automation and Test in Europe, 2004Co-Authors: Todor Stefanov, Bart Kienhuis, Claudiu Zissulescu, Alexandru Turjan, E F DeprettereAbstract:New emerging embedded system platforms in the realm of high-throughput multimedia, imaging, and signal processing will consist of multiple microprocessors and reconfigurable components. One of the major problems is how to program these platforms in a systematic and automated way so as to satisfy the performance need of applications executed on these platforms.In this paper, we present our system design approach as an efficient solution to this programming problem. We show how for an application written in Matlab, a kahn process network specification can automatically be derived and systematically mapped onto a target platform composed of a microprocessor and an FPGA. Furthermore, we illustrate how the mapping approach is applied on a real-life example, namely an M-JPEG encoder.
-
Deprettere, “System design using kahn process networks: The Compaan/Laura approach
2004Co-Authors: Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart KienhuisAbstract:New emerging embedded system platforms in the realm of high-throughput multimedia, imaging, and signal processing will consist of multiple microprocessors and reconfigurable components. One of the major problems is how to program these platforms in a sys-tematic and automated way so as to satisfy the performance need of applications executed on these platforms. In this paper, we present our system design approach as an effi-cient solution to this programming problem. We show how for an application written in Matlab, a kahn process network specifica-tion can automatically be derived and systematically mapped onto a target platform composed of a microprocessor and an FPGA. Furthermore, we illustrate how the mapping approach is applied on a real-life example, namely an M-JPEG encoder. 1
Pieter Van Der Wolf - One of the best experts on this subject based on the ideXlab platform.
-
Y-Chart Based System Level Performance Analysis: An M-JPEG Case Study
2000Co-Authors: Todor Stefanov, Paul Lieverse, Ed Deprettere, Pieter Van Der WolfAbstract:In the Artemis project an architecture workbench is being developed. One of the inputs for defining this workbench is the SPADE methodology. SPADE (System level Performance Analysis and Design space Exploration) follows the Y-chart approach; application and architecture are modeled separately, and the mapping of the application onto the architecture is an explicit design step. As an advantage we can easily modify the application, architecture, or mapping, resulting in a quick turnaround time to explore alternative system implementations. In this paper we introduce and evaluate SPADE through an illustrative case study. In this case study we start from a modified M-JPEG application and map this application onto a shared memory multi-processor architecture. The example system is also used in the Artemis project as a driver and case study for the design and evaluation of the workbench. We define the application as a kahn process network. The architecture and mapping are speci..
-
Y-Chart Based System Level Performance Analysis: An M-JPEG Case Study
2000Co-Authors: Todor Stefanov, Paul Lieverse, Ed Deprettere, Pieter Van Der WolfAbstract:In the Artemis project an architecture workbench is being developed. One of the inputs for defining this workbench is the SPADE methodology. SPADE (System level Performance Analysis and Design space Exploration) follows the Y-chart approach; application and architecture are modeled separately, and the mapping of the application onto the architecture is an explicit design step. As an advantage we can easily modify the application, architecture, or mapping, resulting in a quick turnaround time to explore alternative system implementations. In this paper we introduce and evaluate SPADE through an illustrative case study. In this case study we start from a modified M-JPEG application and map this application onto a shared memory multi-processor architecture. The example system is also used in the Artemis project as a driver and case study for the design and evaluation of the workbench. We define the application as a kahn process network. The architecture and mapping are specified using Sp..
-
An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology
1999Co-Authors: Pieter Van Der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees VissersAbstract:We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology for architecture exploration. The case study demonstrates that this methodology provides a structured approach to the efficient evaluation of the performance of candidate architectures for selected benchmark applications. We learned that the MPEG-2 decoder can conveniently be modeled as a kahn process network using a simple API. Abstract models of architectures can be constructed efficiently using a library of generic building blocks. A trace driven simulation technique enables the use of these abstract models for performance analysis with correct handling of data dependent behavior. We performed a design space exploration to derive how the performance of the decoder depends on the busload and the frame rate
-
An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology
1999Co-Authors: Pieter Van Der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees VissersAbstract:We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology for architecture exploration. The case study demonstrates that this methodology provides a structured approach to the efficient evaluation of the performance of candidate architectures for selected benchmark applications. We learned that the MPEG-2 decoder can conveniently be modeled as a kahn process network using a simple API. Abstract models of architectures can be constructed efficiently using a library of generic building blocks. A trace driven simulation technique enables the use of these abstract models for performance analysis with correct handling of data dependent behavior. We performed a design space exploration to derive how the performance of the decoder depends on the busload and the frame rate. 1 Introduction and Objectives In this paper we focus on the design of heterogeneous systems archite..
Paul Lieverse - One of the best experts on this subject based on the ideXlab platform.
-
Y-Chart Based System Level Performance Analysis: An M-JPEG Case Study
2000Co-Authors: Todor Stefanov, Paul Lieverse, Ed Deprettere, Pieter Van Der WolfAbstract:In the Artemis project an architecture workbench is being developed. One of the inputs for defining this workbench is the SPADE methodology. SPADE (System level Performance Analysis and Design space Exploration) follows the Y-chart approach; application and architecture are modeled separately, and the mapping of the application onto the architecture is an explicit design step. As an advantage we can easily modify the application, architecture, or mapping, resulting in a quick turnaround time to explore alternative system implementations. In this paper we introduce and evaluate SPADE through an illustrative case study. In this case study we start from a modified M-JPEG application and map this application onto a shared memory multi-processor architecture. The example system is also used in the Artemis project as a driver and case study for the design and evaluation of the workbench. We define the application as a kahn process network. The architecture and mapping are speci..
-
Y-Chart Based System Level Performance Analysis: An M-JPEG Case Study
2000Co-Authors: Todor Stefanov, Paul Lieverse, Ed Deprettere, Pieter Van Der WolfAbstract:In the Artemis project an architecture workbench is being developed. One of the inputs for defining this workbench is the SPADE methodology. SPADE (System level Performance Analysis and Design space Exploration) follows the Y-chart approach; application and architecture are modeled separately, and the mapping of the application onto the architecture is an explicit design step. As an advantage we can easily modify the application, architecture, or mapping, resulting in a quick turnaround time to explore alternative system implementations. In this paper we introduce and evaluate SPADE through an illustrative case study. In this case study we start from a modified M-JPEG application and map this application onto a shared memory multi-processor architecture. The example system is also used in the Artemis project as a driver and case study for the design and evaluation of the workbench. We define the application as a kahn process network. The architecture and mapping are specified using Sp..
-
Y-chart based system level performance analysis: an M-JPEG case study
2000Co-Authors: Todor Stefanov, Paul LieverseAbstract:Abstract — In the Artemis project an architecture workbench is being developed. One of the inputs for defining this workbench is the SPADE methodology. SPADE (System level Performance Analysis and Design space Exploration) follows the Y-chart approach; application and architecture are modeled separately, and the mapping of the application onto the architecture is an explicit design step. As an advantage we can easily modify the application, architecture, or mapping, resulting in a quick turnaround time to explore alternative system implementations. In this paper we introduce and evaluate SPADE through an illustrative case study. In this case study we start from a modified M-JPEG application and map this application onto a shared memory multi-processor architecture. The example system is also used in the Artemis project as a driver and case study for the design and evaluation of the workbench. We define the application as a kahn process network. The architecture and mapping are specified using Spade architecture and mapping languages. We present results of simulations for alternative architecture instances and mappings. Keywords—system level design, M-JPEG, design space exploration, signal processing, application modeling, architecture modeling I
-
An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology
1999Co-Authors: Pieter Van Der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees VissersAbstract:We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology for architecture exploration. The case study demonstrates that this methodology provides a structured approach to the efficient evaluation of the performance of candidate architectures for selected benchmark applications. We learned that the MPEG-2 decoder can conveniently be modeled as a kahn process network using a simple API. Abstract models of architectures can be constructed efficiently using a library of generic building blocks. A trace driven simulation technique enables the use of these abstract models for performance analysis with correct handling of data dependent behavior. We performed a design space exploration to derive how the performance of the decoder depends on the busload and the frame rate
-
An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology
1999Co-Authors: Pieter Van Der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees VissersAbstract:We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology for architecture exploration. The case study demonstrates that this methodology provides a structured approach to the efficient evaluation of the performance of candidate architectures for selected benchmark applications. We learned that the MPEG-2 decoder can conveniently be modeled as a kahn process network using a simple API. Abstract models of architectures can be constructed efficiently using a library of generic building blocks. A trace driven simulation technique enables the use of these abstract models for performance analysis with correct handling of data dependent behavior. We performed a design space exploration to derive how the performance of the decoder depends on the busload and the frame rate. 1 Introduction and Objectives In this paper we focus on the design of heterogeneous systems archite..
Lê, Nhat Minh - One of the best experts on this subject based on the ideXlab platform.
-
Les réseaux de processus de kahn : progrès non bloquant, parallélisme, relâchement en mémoire partagée
HAL CCSD, 2016Co-Authors: Lê, Nhat MinhAbstract:In this thesis, we are interested in kahn process networks, a simple yet expressive model of concurrency, and its parallel implementation on modern shared-memory architectures. kahn process networks expose concurrency to the programmer through an arrangement of sequential processes and single-producer single-consumer channels. The focus is on the implementation aspects. Of particular importance to our study are two parameters: lock freedom and relaxed memory. The development of fast andefficient lock-free algorithms ties into concerns of controlled resource consumption and reliable performance on current and future platforms with unfair or skewed scheduling such as virtual machines and GPUs. Our work with relaxed memory models complements this more theoretical approach by offering a window into realistic sharedmemory architectures. We present a new lock-free algorithm for a kahn process network interpreter. It is disjoint-access parallel: we allow multiple threads to work on the same shared kahn process network, fully utilizing the parallelism exhibited by independent processes. It is nonblockingin that it guarantees global progress in bounded memory, even in the presence of (possibly infinite) delays affecting the executing threads. To our knowledge, it is the first lock-free system of this size, and integrates various well-known non-blocking techniques and concepts (e.g., safe memory reclamation, multi-word updates, assistance) with ideas and optimizations specific to the kahn network setting. We also discuss a variant of the algorithm, which is blocking and targeted at high-performance computing, with encouraging experimental results.La thèse porte sur les réseaux de kahn, un modèle de concurrence simple et expressif proposé par Gilles kahn dans les années 70, et leur implémentation sur des architectures multi-coeurs modernes, à mémoire partagée. Dans un réseau de kahn, le programmeur décrit un programme parallèle comme un ensemble de processus et de canaux communicants, reliant chacun exactement un processus producteur à un consommateur. Nous nous concentrons ici sur les aspects algorithmiques et les choix de conception liés à l'implémentation, avec deux points clefs : les garanties non bloquantes et la mémoire relâchée. Le développement d'algorithmes non bloquants efficaces s'inscrit dans une optique de gestion des ressources et de garantie de performance sur les plateformes à ordonnancement irrégulier, telles que les machines virtuelles ou les GPU. Un travail complémentaire sur les modèles de mémoire relâchée vient compléter cette approche théorique par un prolongement plus pratique dans le monde des architectures à mémoire partagée contemporaines. Nous présentons un nouvel algorithme non bloquant pour l'interprétation de réseaux de kahn. Celui-ci est parallèle sur les accès disjoints : il permet à plusieurs processeursde travailler simultanément sur un même réseau de kahn partagé, tout en exploitant le parallélisme entre processus indépendants. Il offre dans le même temps des garanties de progrès non bloquant : en mémoire bornée et en présence de retards sur les processeurs. L'ensemble forme, à notre connaissance, le premier système complètement non bloquant de cette envergure : techniques classiques de programmation non bloquante et contributions spécifiques aux réseaux de kahn. Nous discutons également d'une variante bloquante destinée au calcul haute performance, avec des résultats expérimentaux encourageants
-
Les réseaux de processus de kahn : progrès non bloquant, parallélisme, relâchement en mémoire partagée
HAL CCSD, 2016Co-Authors: Lê, Nhat MinhAbstract:In this thesis, we are interested in kahn process networks, a simple yet expressive model of concurrency, and its parallel implementation on modern shared-memory architectures. kahn process networks expose concurrency to the programmer through an arrangement of sequential processes and single-producer single-consumer channels.The focus is on the implementation aspects. Of particular importance to our study are two parameters: lock freedom and relaxed memory. The development of fast and efficient lock-free algorithms ties into concerns of controlled resource consumption (important in embedded systems) and reliable performance on current and future platforms with unfair or skewed scheduling such as virtual machines and GPUs. Our work with relaxed memory models complements this more theoretical approach by offering a window into realistic shared-memory architectures.We present a new lock-free algorithm for a kahn process network interpreter. It is disjoint-access parallel: we allow multiple threads to work on the same shared kahn process network, fully utilizing the parallelism exhibited by independent processes. It is non-blocking in that it guarantees global progress in bounded memory, even in the presence of (possibly infinite) delays affecting the executing threads. To our knowledge, it is the first lock-free system of this size, and integrates various well-known non-blocking techniques and concepts (e.g., safe memory reclamation, multi-word updates, assistance) with ideas and optimizations specific to the kahn network setting. We also discuss a blocking variant of this algorithm, targetted at high-performance computing, with en-couraging experimental results.La thèse porte sur les réseaux de kahn, un modèle de concurrence simple et expressif proposé par Gilles kahn dans les années 70, et leur implémentation sur des architectures modernes, multi-cœurs et à mémoire partagée. Dans un réseau de kahn, le programmeur décrit un programme parallèle comme un ensemble de processus et de canaux communi- cants, chaque canal reliant exactement un processus producteur à un consommateur.Nous nous concentrons ici sur les aspects algorithmiques et les choix de conception liés à l’implémentation, avec en vue deux paramètres clefs : les garanties non bloquantes (lock freedom) et la mémoire relâchée. Le développement d’algorithmes non bloquants efficaces s’inscrit dans une optique de gestion des ressources (importante pour les systèmes embarqués) et de garantie de performance sur les plateformes à ordonnancement irrégulier, telles que les machines virtuelles ou les processeurs graphiques programmables. Un travail complémentaire sur les modèles de mémoire relâchée vient compléter cette ap- proche théorique par un prolongement plus pratique dans le monde des architectures à mémoire partagée contemporaines.Nous présentons un nouvel algorithme non bloquant pour l’interprétation de réseaux de kahn. Celui-ci est parallèle sur les accès disjoints : il permet à plusieurs processeurs (ou plusieurs threads) de travailler simultanément sur un même réseau de kahn partagé, tout en exploitant le parallélisme inhérent aux processus indépendants. Il offre dans le même temps des garanties de progrès global non bloquant, c’est-à-dire en mémoire bornée et en présence de retards sur les processeurs. L’ensemble forme, à notre connaissance, le premier système complètement non bloquant de cette envergure. Il met en œuvre une pa- lette cohérente de concepts et de techniques classiques de programmation non bloquante (recyclage de la mémoire, mises à jour complexes avec assistance, etc.), et incorpore des idées et optimisations spécifiques aux réseaux de kahn. Nous discutons également d’une variante bloquante destinée au calcul haute performance, avec des résultats expérimentaux encourageants
Neil Bergmann - One of the best experts on this subject based on the ideXlab platform.
-
System Level Design Methodology for Hybrid Multi-processor SoC on FPGA
2008 16th International Symposium on Field-Programmable Custom Computing Machines, 2008Co-Authors: John Williams, Neil BergmannAbstract:In this paper, we present a reconfigurable system on chip design framework that generates an architectural design along with binding and scheduling algorithm, specific to the input application in kahn process network specification.The likelihood that tasks and communication channels may have many potential physical manifestations is explicitly recognised and embraced, to assist the design exploration process. The architectural design, binding and scheduling problems are formulated as a Integer Linear Programming problem, with physical constraints such as available logic resources, computation time and memory footprints to guide the design space exploration.
