The Experts below are selected from a list of 69 Experts worldwide ranked by ideXlab platform
Omer Khan - One of the best experts on this subject based on the ideXlab platform.
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osprey implementation of memory consistency models for Cache coherence protocols involving invalidation free data access
International Conference on Parallel Architectures and Compilation Techniques, 2015Co-Authors: George Kurian, Qingchuan Shi, Srinivas Devadas, Omer KhanAbstract:Data access in modern processors contributes significantly to the overall performance and energy consumption. Traditionally, data is distributed among the cores through an on-chip Cache hierarchy, and each producer/consumer accesses data through its private Level-1 Cache relying on the Cache coherence protocol for consistency. Recently, remote access, a mechanism that reduces energy and latency through word-Level access to data anywhere on chip has been proposed. Remote access does not replicate data in the private Caches, and thereby removes the need for expensive Cache line invalidations or updates. Researchers have implemented remote access as an auxiliary mechanism in Cache coherence to improve efficiency. Unfortunately, stronger memory models, such as Intel's TSO, require strict ordering among the loads and stores. This introduces serialization penalties for data classified to be accessed remotely, which hampers each core's ability to optimally exploit memory Level parallelism. In this paper we propose a novel timestamp-based scheme to detect memory consistency violations. The proposed scheme enables remote accesses to be issued and completed in parallel while continuously detecting whether any ordering violations have occurred, and rolling back the pipeline state (if needed). We implement our scheme for the locality-aware Cache coherence protocol that uses remote access as an auxiliary mechanism for efficient data access. Our evaluation using a 64-core multicore processor with out-of-order speculative cores shows that the proposed technique improves completion time by 26% and energy by 20% over a state-of-the-art Cache management scheme.
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nuca l1 a non uniform access latency Level 1 Cache architecture for multicores operating at near threshold voltages
ACM Transactions on Architecture and Code Optimization, 2014Co-Authors: Farrukh Hijaz, Omer KhanAbstract:Research has shown that operating in the near-threshold region is expected to provide up to 10× energy efficiency for future processors. However, reliable operation below a minimum voltage (Vccmin) cannot be guaranteed due to process variations. Because SRAM margins can easily be violated at near-threshold voltages, their bit-cell failure rates are expected to rise steeply. Multicore processors rely on fast private L1 Caches to exploit data locality and achieve high performance. In the presence of high bit-cell fault rates, traditionally an L1 Cache either sacrifices capacity or incurs additional latency to correct the faults. We observe that L1 Cache sensitivity to hit latency offers a design trade-off between capacity and latency. When fault rate is high at extreme Vccmin, it is beneficial to recover L1 Cache capacity, even if it comes at the cost of additional latency. However, at low fault rates, the additional constant latency to recover Cache capacity degrades performance. With this trade-off in mind, we propose a Non-Uniform Cache Access L1 architecture (NUCA-L1) that avoids additional latency on accesses to fault-free Cache lines. To mitigate the capacity bottleneck, it deploys a correction mechanism to recover capacity at the cost of additional latency. Using extensive simulations of a 64-core multicore, we demonstrate that at various bit-cell fault rates, our proposed private NUCA-L1 Cache architecture performs better than state-of-the-art schemes, along with a significant reduction in energy consumption.
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a private Level 1 Cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near threshold voltages
International Conference on Computer Design, 2013Co-Authors: Farrukh Hijaz, Qingchuan Shi, Omer KhanAbstract:Near-threshold voltage (NTV) operation is expected to enable up to 10× energy-efficiency for future processors. However, reliable operation below a minimum voltage (Vccmin) cannot be guaranteed. Specifically, SRAM bit-cell error rates are expected to rise steeply since their margins can easily be violated at near-threshold voltages. Multicore processors rely on fast private L1 Caches to exploit data locality and achieve high performance. In the presence of high bit-cell error rates, an L1 Cache can either sacrifice capacity or incur additional latency to correct the errors. We observe that L1 Cache sensitivity to hit latency offers a design tradeoff between capacity and latency. When error rate is high at extreme Vccmin, it is worthwhile incurring additional latency to recover and utilize the additional L1 Cache capacity. However, at low error rates, the additional constant latency to recover Cache capacity degrades performance. With this tradeoff in mind, we propose a novel private L1 Cache architecture that dynamically learns and adapts by either recovering Cache capacity at the cost of additional latency overhead, or operate at lower capacity while utilizing the benefits of optimal hit latency. Using simulations of a 64-core multicore, we demonstrate that our adaptive L1 Cache architecture performs better than both individual schemes at low and high error rates (i.e., various NTV conditions).
Qingchuan Shi - One of the best experts on this subject based on the ideXlab platform.
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osprey implementation of memory consistency models for Cache coherence protocols involving invalidation free data access
International Conference on Parallel Architectures and Compilation Techniques, 2015Co-Authors: George Kurian, Qingchuan Shi, Srinivas Devadas, Omer KhanAbstract:Data access in modern processors contributes significantly to the overall performance and energy consumption. Traditionally, data is distributed among the cores through an on-chip Cache hierarchy, and each producer/consumer accesses data through its private Level-1 Cache relying on the Cache coherence protocol for consistency. Recently, remote access, a mechanism that reduces energy and latency through word-Level access to data anywhere on chip has been proposed. Remote access does not replicate data in the private Caches, and thereby removes the need for expensive Cache line invalidations or updates. Researchers have implemented remote access as an auxiliary mechanism in Cache coherence to improve efficiency. Unfortunately, stronger memory models, such as Intel's TSO, require strict ordering among the loads and stores. This introduces serialization penalties for data classified to be accessed remotely, which hampers each core's ability to optimally exploit memory Level parallelism. In this paper we propose a novel timestamp-based scheme to detect memory consistency violations. The proposed scheme enables remote accesses to be issued and completed in parallel while continuously detecting whether any ordering violations have occurred, and rolling back the pipeline state (if needed). We implement our scheme for the locality-aware Cache coherence protocol that uses remote access as an auxiliary mechanism for efficient data access. Our evaluation using a 64-core multicore processor with out-of-order speculative cores shows that the proposed technique improves completion time by 26% and energy by 20% over a state-of-the-art Cache management scheme.
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a private Level 1 Cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near threshold voltages
International Conference on Computer Design, 2013Co-Authors: Farrukh Hijaz, Qingchuan Shi, Omer KhanAbstract:Near-threshold voltage (NTV) operation is expected to enable up to 10× energy-efficiency for future processors. However, reliable operation below a minimum voltage (Vccmin) cannot be guaranteed. Specifically, SRAM bit-cell error rates are expected to rise steeply since their margins can easily be violated at near-threshold voltages. Multicore processors rely on fast private L1 Caches to exploit data locality and achieve high performance. In the presence of high bit-cell error rates, an L1 Cache can either sacrifice capacity or incur additional latency to correct the errors. We observe that L1 Cache sensitivity to hit latency offers a design tradeoff between capacity and latency. When error rate is high at extreme Vccmin, it is worthwhile incurring additional latency to recover and utilize the additional L1 Cache capacity. However, at low error rates, the additional constant latency to recover Cache capacity degrades performance. With this tradeoff in mind, we propose a novel private L1 Cache architecture that dynamically learns and adapts by either recovering Cache capacity at the cost of additional latency overhead, or operate at lower capacity while utilizing the benefits of optimal hit latency. Using simulations of a 64-core multicore, we demonstrate that our adaptive L1 Cache architecture performs better than both individual schemes at low and high error rates (i.e., various NTV conditions).
George Kurian - One of the best experts on this subject based on the ideXlab platform.
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osprey implementation of memory consistency models for Cache coherence protocols involving invalidation free data access
International Conference on Parallel Architectures and Compilation Techniques, 2015Co-Authors: George Kurian, Qingchuan Shi, Srinivas Devadas, Omer KhanAbstract:Data access in modern processors contributes significantly to the overall performance and energy consumption. Traditionally, data is distributed among the cores through an on-chip Cache hierarchy, and each producer/consumer accesses data through its private Level-1 Cache relying on the Cache coherence protocol for consistency. Recently, remote access, a mechanism that reduces energy and latency through word-Level access to data anywhere on chip has been proposed. Remote access does not replicate data in the private Caches, and thereby removes the need for expensive Cache line invalidations or updates. Researchers have implemented remote access as an auxiliary mechanism in Cache coherence to improve efficiency. Unfortunately, stronger memory models, such as Intel's TSO, require strict ordering among the loads and stores. This introduces serialization penalties for data classified to be accessed remotely, which hampers each core's ability to optimally exploit memory Level parallelism. In this paper we propose a novel timestamp-based scheme to detect memory consistency violations. The proposed scheme enables remote accesses to be issued and completed in parallel while continuously detecting whether any ordering violations have occurred, and rolling back the pipeline state (if needed). We implement our scheme for the locality-aware Cache coherence protocol that uses remote access as an auxiliary mechanism for efficient data access. Our evaluation using a 64-core multicore processor with out-of-order speculative cores shows that the proposed technique improves completion time by 26% and energy by 20% over a state-of-the-art Cache management scheme.
Abu Asaduzzaman - One of the best experts on this subject based on the ideXlab platform.
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Cache Optimization for Mobile Devices Running Multimedia Applications
2016Co-Authors: Abu Asaduzzaman, Imad Mahgoub, Praveen Sanigepalli, Hari Kalva, Ravi Shankar, Borko FurhtAbstract:The popularity of mobile/wireless embedded systems running multimedia applications is growing. MPEG4 is an important and demanding multimedia application. With improved CPU, memory subsystem deficiency is the major barrier to improving the system performance. Studies show that there is sufficient reuse of values for caching to significantly reduce the raw required memory bandwidth for video data. Decoding MPEG4 video data in software generates many times more Cache-memory traffic than required. Proper understanding of the decoding algorithm and the composition of its data set is obvious to improve the performance of such a system. The focus of this paper is to enhance MPEG4 decoding performance through Cache optimization of a mobile device. The architecture we simulate includes a digital signal processor (DSP) to run the decoding algorithm and a two-Level Cache system. Level-1 Cache is split into Data (D1) and Instruction (I1) Caches and Level-2 (CL2) is a unified Cache. We use Cachegrind and VisualSim simulation tools to optimize Cache size, line size, associativity, and Levels of Caches for a wireless device decoding MPEG4 video. 1
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on Level 1 Cache locking for high performance low power real time multicore systems
Computers & Electrical Engineering, 2013Co-Authors: Abu Asaduzzaman, Vidya Suryanarayana, Fadi N SibaiAbstract:Abstract Multiple Caches in multicore architecture increase power consumption and timing unpredictability. Although Cache locking in single-core systems shows improvement for large multithreaded applications, there is no such effective strategy for multicore systems. In this work, we propose three Level-1 Cache locking strategies for multicore systems – static, random, and dynamic. In the random strategy, blocks are randomly selected for locking. The static and dynamic schemes are based on the analysis of applications’ worst case execution time (WCET). The static scheme does not allow unlocking blocks during runtime, but the dynamic scheme does. Using VisualSim and Heptane tools, we simulate a system with four cores and two Levels of Caches. According to the simulation results, the dynamic Cache locking strategy outperforms the static and random strategies by up to 35% in mean delay per task and up to 22% in total power consumption for the workloads used (e.g., MPEG3 and MPEG4).
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an effective Level 1 Cache locking strategy for energy efficient real time multicore systems
Computer and Information Technology, 2011Co-Authors: Abu AsaduzzamanAbstract:Multicore architectures with multiLevel Caches are being used in both desktop and embedded processors for their improved performance. Caches increase execution time unpredictability and make it difficult to support real-time applications. Caches also challenge the power supply system by consuming a lot of power. Studies show that Cache locking improves predictability and performance/power ratio for single-core systems. Recent studies also show that way Cache locking can be applied in multicore systems. In this work, we propose a simple but effective Level-1 wayc ache locking scheme for multicore systems. This scheme is based on the analysis of applications' worst case execution time (WCET) and it allows changing the locked Cache size during runtime to achieve the optimal predictability and performance/power ratio for the running application. Using Heptane WCET analyzer, we study MPEG4, H.264/AVC, FFT, MI, and DFT codes and generate workloads. Workloads provide miss information for the memory blocks (without Cache locking). Using VisualSim tool, we model and simulate a system with four cores and two Levels of Caches. We also simulate a random Cache locking strategy. Experimental results show that our Cache locking scheme significantly improves predictability by decreasing total misses more than 50%. Experimental results also show that our proposed Cache locking strategy outperforms the random strategy by up to 22%.
Lawrence T Clark - One of the best experts on this subject based on the ideXlab platform.
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a low power 2 5 ghz 90 nm Level 1 Cache and memory management unit
IEEE Journal of Solid-state Circuits, 2005Co-Authors: J R Haigh, Michael Wilkerson, J B Miller, Timothy S Beatty, S Strazdus, Lawrence T ClarkAbstract:The design of a 90-nm virtually addressed Cache subsystem with separate 32-kB instruction and data Caches is described. The circuits and microarchitecture are illustrated, including architecture Level trace data validating low-power features and provisions to support snooping while maintaining the latency and power of virtual addressing. Low-power memory management unit design including a translation lookaside buffer with process identifier mapping is also described. Level 1 Caches with support for high bandwidth, single cycle 256 bit fill and evict, as well as features for low power are also described. The design approaches are validated through both simulation and experimental results.