The Experts below are selected from a list of 325623 Experts worldwide ranked by ideXlab platform

B W Williams - One of the best experts on this subject based on the ideXlab platform.

  • quasi two Level Operation of modular multiLevel converter for use in a high power dc transformer with dc fault isolation capability
    IEEE Transactions on Power Electronics, 2015
    Co-Authors: I A Gowaid, G P Adam, Ahmed M Massoud, Shehab Ahmed, Derrick Holliday, B W Williams
    Abstract:

    DC fault protection is one challenge impeding the development of multi-terminal DC grids. The absence of manufacturing and Operational standards has led to many point-to-point HVDC links built at different voltage Levels, which creates another challenge. Therefore, the issues of voltage matching and DC fault isolation are undergoing extensive research and are addressed in this paper. A quasi two-Level operating mode of the modular multiLevel converter is proposed, where the converter generates a square wave with controllable dv/dt by employing the cell voltages to create transient intermediate voltage Levels. Cell capacitance requirements diminish and the footprint of the converter is reduced. The common-mode DC component in the arm currents is not present in the proposed operating mode. The converter is proposed as the core of a DC to DC transformer where two converters operating in the proposed mode are coupled by an AC transformer for voltage matching and galvanic isolation. The proposed DC transformer is shown to be suitable for high-voltage high-power applications due to the low switching frequency, high efficiency, modularity, and reliability. The DC transformer facilitates DC voltage regulation and near instant isolation of DC faults within its protection zone. Analysis and simulations confirm these capabilities in a system-oriented approach.

  • Modular multiLevel structure of a high power dual active bridge DC transformer with stepped two-Level output
    2014 16th European Conference on Power Electronics and Applications, 2014
    Co-Authors: I A Gowaid, G P Adam, A. M. Massoud, S. Ahmed, D. Holliday, B W Williams
    Abstract:

    This paper addresses the issues of dc voltage matching and dc fault protection in potential super-grids. An approach for high power dc-dc conversion is proposed and analyzed. A front-to-front connection of modular-multiLevel converters (MMC) forms a dual active bridge (DAB)-like structure. Near two-Level Operation is achieved by sequential switching of half-bridge chopper cells. This alleviates dv/dt stress exercised by two-Level DAB configurations on the ac stage. The operating mode, switching patterns necessary are distinct from conventional MMC. Furthermore, common-mode currents, cell capacitance size, arm inductances are significantly reduced. The considered structure is shown to be useful for high power applications due to the low switching frequency, modularity, reliability and dc fault isolation capability. Various Operation aspects are illustrated using simulations. A reduced-scale test rig provides an experimental proof of the concept.

  • quasi two Level and three Level Operation of a diode clamped multiLevel inverter using space vector modulation
    Iet Power Electronics, 2012
    Co-Authors: G P Adam, S J Finney, Olorunfemi Ojo, B W Williams
    Abstract:

    This study presents space vector-based quasi-two-Level Operation of a diode-clamped multiLevel inverter which improves dc link utilisation and output voltage quality, and avoids the dc link capacitor voltage balancing problem experienced with standard multiLevel Operation. Beside a review of quasi-two-Level Operation and the capacitor voltage balancing method, the study presents a detailed discussion on the implementation of space vector modulation and the selection of switching sequence for a five-Level inverter. Additionally, the condition for maximum theoretical modulation index for space vector modulation is established. A prototype five-Level diode-clamped inverter is to experimentally validate the approach. Also this study extends the concept of quasi-two-Level-to-three-Level Operation of the diode-clamped multiLevel inverter in order to address the shortcomings experienced with quasi-two-Level Operation, such as low waveform quality and high switching losses. The validity of three-Level inverter Operation is confirmed experimentally on a prototype of a five-Level diode-clamped inverter. The study also highlights the limitations of three-Level Operation of a diode-clamped multiLevel inverter.

Jhyy Cheng Liou - One of the best experts on this subject based on the ideXlab platform.

  • optimized ono thickness for multi Level and 2 bit cell Operation for wrapped select gate wsg sonos memory
    Semiconductor Science and Technology, 2008
    Co-Authors: Tiensheng Chao, Wuchin Peng, Wenluh Yang, Jianhao Chen, Tsungyu Yang, Tsungmin Hsieh, Chaosung Lai, Ming Wen, Chienhsing Lee, Jhyy Cheng Liou
    Abstract:

    In this paper, highly reliable wrapped-select-gate (WSG) silicon–oxide–nitride–oxide–silicon (SONOS) memory cells with multi-Level and 2-bit/cell Operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-Level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-Level Operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

Tiensheng Chao - One of the best experts on this subject based on the ideXlab platform.

  • optimized ono thickness for multi Level and 2 bit cell Operation for wrapped select gate wsg sonos memory
    Semiconductor Science and Technology, 2008
    Co-Authors: Tiensheng Chao, Wuchin Peng, Wenluh Yang, Jianhao Chen, Tsungyu Yang, Tsungmin Hsieh, Chaosung Lai, Ming Wen, Chienhsing Lee, Jhyy Cheng Liou
    Abstract:

    In this paper, highly reliable wrapped-select-gate (WSG) silicon–oxide–nitride–oxide–silicon (SONOS) memory cells with multi-Level and 2-bit/cell Operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-Level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-Level Operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

  • a highly reliable multi Level and 2 bit cell Operation of wrapped select gate wsg sonos memory with optimized ono thickness
    International Symposium on VLSI Technology Systems and Applications, 2007
    Co-Authors: Tiensheng Chao, Wuchin Peng, Wenluh Yang, Jerchyi Wang, Jianhao Chen, Tsungyu Yang, Chaosung Lai, Tzuping Chen, Chienhung Chen, Chihhung Lin
    Abstract:

    High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-Level and 2-bit/cell Operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-Level storage is easily obtained and well Vth distribution is also presented. High program/erase speed (10 us/5 ms) and low programming current (3.5 u/A) are performed to achieve the multi-Level Operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.

  • ahighly reliable multi Level and2 bit cell Operation ofwrapped select gate wsg sonos
    2007
    Co-Authors: Tiensheng Chao, Jerchyi Wang, Jianhao Chen, Chaosung Lai, Tzuping Chen, Chienhung Chen, Chihhung Lin
    Abstract:

    electric field atp-njunction, whileforthethickONO stacks High-performance wrapped-select-gate (WSG) SONGS (60/80/100), theelectric field atthegapincreased gradually asshown (silicon-oxide-nitride-silicon) memorycells withmulti-Level and inFig. 5. 2-bit/cell Operation havebeensuccessfully demonstrated. The Figures 6 and7 demonstrated thedrain andgatedisturbance source-side injection mechanism withdifferent ONO thickness in performance oftheWSG-SONOSmemorywithdifferent ONO WSG-SONOS memorywas wellinvestigated. The differentthickness forthe multi-Level Operation, respectively. Fromthese figures, programming efficiency oftheWSG-SONOSmemorywithdifferentwecaneasily observe that thethick topoxide will contribute tobetter ONO thickness canbeexplained bythelateral electrical field extractedgate disturbance while thedrain disturbance isnotaffected bytheONO fromthesimulation. Furthermore, multi-Level storage iseasily obtainedthickness. Moreover, thethin bottom oxide exhibits better P/E cycling andwellVthdistribution isalso presented. Highprogram/erase speed performance resulted intheVFl shift owingtotheless interface states (1Ous/5ms) andlowprogramming current (3.5uA) areperformed to generation asindicated inFig.8.To sumup,theONO thickness achieve themulti-Level Operation withexcellent gateanddrain (50/80/100) usedintheWSG-SONOSmemoryshould beoptimized to disturbance, second-bit effect, data retention andendurance. gethighperformance andbetter reliability.

Xu Cai - One of the best experts on this subject based on the ideXlab platform.

  • stepped 2 Level Operation of three port modular dc dc converter applied in hvdc application
    IEEE Access, 2018
    Co-Authors: Hongcheng You, Xu Cai
    Abstract:

    High-voltage dc/dc converter is the key equipment to interconnect high-voltage dc (HVdc) systems with different voltage Levels and to build dc grid. This paper presents a novel three-port modular dc/dc converter (TP-MDCC) to interconnect three HVdc systems, and it offers the following merits: 1) high efficiency for the elimination of multiple dc/ac conversion stages and transformers; 2) modular design and small submodule (SM) capacitance requirement; 3) low $\text{d}v/\text{d}t$ stress; and 4) the sorting algorithm of the SM capacitor voltages needs only to be executed twice in a period, which poses small computation burden. In this paper, the Operation principle and the control strategy of the TP-MDCC are analyzed, and the simulation and experimental results verify the effectiveness of the converter.

T C Green - One of the best experts on this subject based on the ideXlab platform.

  • trapezoidal current modulation for bidirectional high step ratio modular dc dc converters
    IEEE Transactions on Power Electronics, 2020
    Co-Authors: Yang Qiao, Xiaotian Zhang, Xin Xiang, Xu Yang, T C Green
    Abstract:

    A modular dc–dc converter (MDCC) has been proposed for high-step-ratio interconnection in dc grid applications. To further optimize the performance of the MDCC, this article presents a trapezoidal current modulation with bidirectional power flow ability. By giving all the submodule (SM) capacitors an equal duty to withstand the stack dc voltage, their voltages are balanced without additional feedback control. Moreover, based on soft-switching performance and circulating current analysis, three-Level and two-Level Operation modes featured with high efficiency conversion and large power transmission, respectively, are introduced. The control schemes of both modes are designed to minimize the conduction losses. Besides, the SM capacitor voltage ripples with different switching patterns are compared, and the option for ripple minimization is presented. A full-scale case study is provided to introduce the design process and device selection of the MDCC. The experimental tests based on a downscaled prototype are finally presented to validate the theoretical analysis.