Linear Address

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The Experts below are selected from a list of 42 Experts worldwide ranked by ideXlab platform

Wooyoung Jang - One of the best experts on this subject based on the ideXlab platform.

  • Adaptive Linear Address Map for Bank Interleaving in DRAMs
    IEEE Access, 2019
    Co-Authors: Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang
    Abstract:

    The conventional Linear Address map can degrade memory utilization and system performance when an access pattern is not Linear. To improve memory system performance, the adaptive bank-interleaved Linear Address map for a DRAM technology is proposed. In our approach, the Addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the Address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed Address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost.

Jae Young Hur - One of the best experts on this subject based on the ideXlab platform.

  • Adaptive Linear Address Map for Bank Interleaving in DRAMs
    IEEE Access, 2019
    Co-Authors: Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang
    Abstract:

    The conventional Linear Address map can degrade memory utilization and system performance when an access pattern is not Linear. To improve memory system performance, the adaptive bank-interleaved Linear Address map for a DRAM technology is proposed. In our approach, the Addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the Address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed Address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost.

Gayathri Nagabhushan - One of the best experts on this subject based on the ideXlab platform.

  • a hypervisor based system for protecting software runtime memory and persistent storage
    Spring Simulation Multiconference, 2008
    Co-Authors: Prashant Dewan, David M Durham, Hormuzd M Khosravi, Men Long, Gayathri Nagabhushan
    Abstract:

    An important goal of software security is to ensure sensitive/secret data owned by a program shall be exclusively accessible by the program. An obstacle to such security goal is that modern commodity operating systems (OS) for the sake of speed and flexibility have a unified Linear Address space--any OS kernel program can access all the Linear Addresses. As a result, rootkits or malicious system software are able to control the OS virtual Address space, harvest the sensitive data used by software programs on the compromised computer, and report the data to remote entities controlled by hackers. In this paper, we present a holistic approach against sophisticated malware. Instead of focusing on the security of various abstraction layers of OS, we utilize the hardware techniques to directly provide the trust services to software programs. Without modifying OS, we leverage the virtual machine monitor technologies to create a lightweight hypervisor for fine-grain software runtime memory protection. As a result, a program's memory could be hidden from other high privilege system software in a single commodity OS. In addition, we propose the data locker component in the hypervisor, which prevents the sensitive data of software program in persistent storage from leaking to rootkits or other malware. For the performance evaluation, the implementation based on hardware-assisted x86 virtualization technology is presented and experimental results are reported.

Beom Hak Lee - One of the best experts on this subject based on the ideXlab platform.

  • Adaptive Linear Address Map for Bank Interleaving in DRAMs
    IEEE Access, 2019
    Co-Authors: Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang
    Abstract:

    The conventional Linear Address map can degrade memory utilization and system performance when an access pattern is not Linear. To improve memory system performance, the adaptive bank-interleaved Linear Address map for a DRAM technology is proposed. In our approach, the Addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the Address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed Address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost.

Sang Woo Rhim - One of the best experts on this subject based on the ideXlab platform.

  • Adaptive Linear Address Map for Bank Interleaving in DRAMs
    IEEE Access, 2019
    Co-Authors: Jae Young Hur, Sang Woo Rhim, Beom Hak Lee, Wooyoung Jang
    Abstract:

    The conventional Linear Address map can degrade memory utilization and system performance when an access pattern is not Linear. To improve memory system performance, the adaptive bank-interleaved Linear Address map for a DRAM technology is proposed. In our approach, the Addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the Address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed Address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost.