The Experts below are selected from a list of 48 Experts worldwide ranked by ideXlab platform

Mladen Berekovic - One of the best experts on this subject based on the ideXlab platform.

  • NORCAS - MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements
    2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019
    Co-Authors: Philipp Jungklass, Mladen Berekovic
    Abstract:

    Modern multicore microcontrollers for systems with hard real-time requirements increasingly use a complex memory hierarchy to improve available performance and distribute competing accesses to separate memories. With the additional computing power available, the complexity of the implemented software has also increased. These two factors make an optimized distribution of the existing software to the available memory an increasing problem for the integration into such systems. Therefore, this article presents an algorithm that calculates an optimized memory distribution based on the microcontroller used, a recording of the code execution on the target hardware, a system deScription and automatically generates the corresponding Linker Script.

  • MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements
    2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019
    Co-Authors: Philipp Jungklass, Mladen Berekovic
    Abstract:

    Modern multicore microcontrollers for systems with hard real-time requirements increasingly use a complex memory hierarchy to improve available performance and distribute competing accesses to separate memories. With the additional computing power available, the complexity of the implemented software has also increased. These two factors make an optimized distribution of the existing software to the available memory an increasing problem for the integration into such systems. Therefore, this article presents an algorithm that calculates an optimized memory distribution based on the microcontroller used, a recording of the code execution on the target hardware, a system deScription and automatically generates the corresponding Linker Script.

Philipp Jungklass - One of the best experts on this subject based on the ideXlab platform.

  • NORCAS - MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements
    2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019
    Co-Authors: Philipp Jungklass, Mladen Berekovic
    Abstract:

    Modern multicore microcontrollers for systems with hard real-time requirements increasingly use a complex memory hierarchy to improve available performance and distribute competing accesses to separate memories. With the additional computing power available, the complexity of the implemented software has also increased. These two factors make an optimized distribution of the existing software to the available memory an increasing problem for the integration into such systems. Therefore, this article presents an algorithm that calculates an optimized memory distribution based on the microcontroller used, a recording of the code execution on the target hardware, a system deScription and automatically generates the corresponding Linker Script.

  • MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time Requirements
    2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2019
    Co-Authors: Philipp Jungklass, Mladen Berekovic
    Abstract:

    Modern multicore microcontrollers for systems with hard real-time requirements increasingly use a complex memory hierarchy to improve available performance and distribute competing accesses to separate memories. With the additional computing power available, the complexity of the implemented software has also increased. These two factors make an optimized distribution of the existing software to the available memory an increasing problem for the integration into such systems. Therefore, this article presents an algorithm that calculates an optimized memory distribution based on the microcontroller used, a recording of the code execution on the target hardware, a system deScription and automatically generates the corresponding Linker Script.

Soonhoi Ha - One of the best experts on this subject based on the ideXlab platform.

  • Dynamic Code Overlay of SDF-Modeled Programs on Low-end Embedded Systems
    Proceedings of the Design Automation & Test in Europe Conference, 2006
    Co-Authors: Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Soonhoi Ha
    Abstract:

    In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF)-modeled program for low-end embedded systems which lack MMU-support. With this technique, the system can utilize expensive SRAM memory more efficiently by using flash memory as code storage. SRAM is divided into several regions called overlay slots. A data-flow block or a cluster of data-flow blocks is loaded into the corresponding overlay slot on demand at run-time. Which blocks are clustered together and which overlay slots are allocated to the clusters are statically decided by the clustering and placement algorithm. We also propose an automatic code generation framework that generates the C-program code, dynamic loader and Linker Script files from the given SDF-modeled blocks and schematic, so we can run or simulate the program immediately without any additional coding effort. Experiments report that we can reduce the SRAM size significantly with a reasonable amount of time overhead for several real applications

  • DATE - Dynamic Code Overlay of SDF-Modeled Programs on Low-end Embedded Systems
    Proceedings of the Design Automation & Test in Europe Conference, 2006
    Co-Authors: Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Soonhoi Ha
    Abstract:

    In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF)–modeled program for low-end embedded systems which lack MMU-support. With this technique, the system can utilize expensive SRAM memory more efficiently by using flash memory as code storage. SRAM is divided into several regions called overlay slots. A data-flow block or a cluster of data-flow blocks is loaded into the corresponding overlay slot on demand at run-time. Which blocks are clustered together and which overlay slots are allocated to the clusters are statically decided by the clustering and placement algorithm. We also propose an automatic code generation framework that generates the C-program code, dynamic loader and Linker Script files from the given SDF-modeled blocks and schematic, so we can run or simulate the program immediately without any additional coding effort. Experiments report that we can reduce the SRAM size significantly with a reasonable amount of time overhead for several real applications.

Mark R. Tuttle - One of the best experts on this subject based on the ideXlab platform.

  • Model checking boot code from AWS data centers
    Formal Methods in System Design, 2020
    Co-Authors: Byron Cook, Kareem Khazem, Michael Tautschnig, Serdar Tasiran, Daniel Kroening, Mark R. Tuttle
    Abstract:

    This paper describes our experience with symbolic model checking in an industrial setting. We have proved that the initial boot code running in data centers at Amazon Web Services is memory safe, an essential step in establishing the security of any data center. Standard static analysis tools cannot be easily used on boot code without modification owing to issues not commonly found in higher-level code, including memory-mapped device interfaces, byte-level memory access, and Linker Scripts. This paper describes automated solutions to these issues and their implementation in the C Bounded Model Checker (CBMC). CBMC is now the first source-level static analysis tool to extract the memory layout described in a Linker Script for use in its analysis.

  • CAV (2) - Model Checking Boot Code from AWS Data Centers
    Computer Aided Verification, 2018
    Co-Authors: Byron Cook, Kareem Khazem, Michael Tautschnig, Serdar Tasiran, Daniel Kroening, Mark R. Tuttle
    Abstract:

    This paper describes our experience with symbolic model checking in an industrial setting. We have proved that the initial boot code running in data centers at Amazon Web Services is memory safe, an essential step in establishing the security of any data center. Standard static analysis tools cannot be easily used on boot code without modification owing to issues not commonly found in higher-level code, including memory-mapped device interfaces, byte-level memory access, and Linker Scripts. This paper describes automated solutions to these issues and their implementation in the C Bounded Model Checker (CBMC). CBMC is now the first source-level static analysis tool to extract the memory layout described in a Linker Script for use in its analysis.

  • Model checking boot code from AWS data centers
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2018
    Co-Authors: Byron Cook, Kareem Khazem, Michael Tautschnig, Serdar Tasiran, Daniel Kroening, Mark R. Tuttle
    Abstract:

    © The Author(s) 2018. This paper describes our experience with symbolic model checking in an industrial setting. We have proved that the initial boot code running in data centers at Amazon Web Services is memory safe, an essential step in establishing the security of any data center. Standard static analysis tools cannot be easily used on boot code without modification owing to issues not commonly found in higher-level code, including memory-mapped device interfaces, byte-level memory access, and Linker Scripts. This paper describes automated solutions to these issues and their implementation in the C Bounded Model Checker (CBMC). CBMC is now the first source-level static analysis tool to extract the memory layout described in a Linker Script for use in its analysis.

Hae-woo Park - One of the best experts on this subject based on the ideXlab platform.

  • Dynamic Code Overlay of SDF-Modeled Programs on Low-end Embedded Systems
    Proceedings of the Design Automation & Test in Europe Conference, 2006
    Co-Authors: Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Soonhoi Ha
    Abstract:

    In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF)-modeled program for low-end embedded systems which lack MMU-support. With this technique, the system can utilize expensive SRAM memory more efficiently by using flash memory as code storage. SRAM is divided into several regions called overlay slots. A data-flow block or a cluster of data-flow blocks is loaded into the corresponding overlay slot on demand at run-time. Which blocks are clustered together and which overlay slots are allocated to the clusters are statically decided by the clustering and placement algorithm. We also propose an automatic code generation framework that generates the C-program code, dynamic loader and Linker Script files from the given SDF-modeled blocks and schematic, so we can run or simulate the program immediately without any additional coding effort. Experiments report that we can reduce the SRAM size significantly with a reasonable amount of time overhead for several real applications

  • DATE - Dynamic Code Overlay of SDF-Modeled Programs on Low-end Embedded Systems
    Proceedings of the Design Automation & Test in Europe Conference, 2006
    Co-Authors: Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Soonhoi Ha
    Abstract:

    In this paper we propose a dynamic code overlay technique of synchronous data-flow (SDF)–modeled program for low-end embedded systems which lack MMU-support. With this technique, the system can utilize expensive SRAM memory more efficiently by using flash memory as code storage. SRAM is divided into several regions called overlay slots. A data-flow block or a cluster of data-flow blocks is loaded into the corresponding overlay slot on demand at run-time. Which blocks are clustered together and which overlay slots are allocated to the clusters are statically decided by the clustering and placement algorithm. We also propose an automatic code generation framework that generates the C-program code, dynamic loader and Linker Script files from the given SDF-modeled blocks and schematic, so we can run or simulate the program immediately without any additional coding effort. Experiments report that we can reduce the SRAM size significantly with a reasonable amount of time overhead for several real applications.