The Experts below are selected from a list of 33 Experts worldwide ranked by ideXlab platform

Qiu Judy - One of the best experts on this subject based on the ideXlab platform.

  • Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture
    'Institute of Electrical and Electronics Engineers (IEEE)', 2019
    Co-Authors: Jiang Lei, Chen Langshi, Qiu Judy
    Abstract:

    Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. Among emerging killer applications, parallel graph processing has been a critical technique to analyze connected data. In this paper, we empirically evaluate various computing platforms including an Intel Xeon E5 CPU, a Nvidia Geforce GTX1070 GPU and an Xeon Phi 7210 processor codenamed Knights Landing (KNL) in the domain of parallel graph processing. We show that the KNL gains encouraging performance when processing graphs, so that it can become a promising solution to accelerating multi-threaded graph applications. We further characterize the impact of KNL architectural enhancements on the performance of a state-of-the art graph framework.We have four key observations: 1 Different graph applications require distinctive numbers of threads to reach the peak performance. For the same application, various datasets need even different numbers of threads to achieve the best performance. 2 Only a few graph applications benefit from the high bandwidth MCDRAM, while others favor the low latency DDR4 DRAM. 3 Vector processing units executing AVX512 SIMD instructions on KNLs are underutilized when running the state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering the lowest Local Memory Access latency hurts the performance of graph benchmarks that are lack of NUMA awareness. At last, We suggest future works including system auto-tuning tools and graph framework optimizations to fully exploit the potential of KNL for parallel graph processing.Comment: published as L. Jiang, L. Chen and J. Qiu, "Performance Characterization of Multi-threaded Graph Processing Applications on Many-Integrated-Core Architecture," 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, United Kingdom, 2018, pp. 199-20

  • Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture
    2019
    Co-Authors: Jiang Lei, Chen Langshi, Qiu Judy
    Abstract:

    Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. Among emerging killer applications, parallel graph processing has been a critical technique to analyze connected data. In this paper, we empirically evaluate various computing platforms including an Intel Xeon E5 CPU, a Nvidia Geforce GTX1070 GPU and an Xeon Phi 7210 processor codenamed Knights Landing (KNL) in the domain of parallel graph processing. We show that the KNL gains encouraging performance when processing graphs, so that it can become a promising solution to accelerating multi-threaded graph applications. We further characterize the impact of KNL architectural enhancements on the performance of a state-of-the art graph framework.We have four key observations: 1 Different graph applications require distinctive numbers of threads to reach the peak performance. For the same application, various datasets need even different numbers of threads to achieve the best performance. 2 Only a few graph applications benefit from the high bandwidth MCDRAM, while others favor the low latency DDR4 DRAM. 3 Vector processing units executing AVX512 SIMD instructions on KNLs are underutilized when running the state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering the lowest Local Memory Access latency hurts the performance of graph benchmarks that are lack of NUMA awareness. At last, We suggest future works including system auto-tuning tools and graph framework optimizations to fully exploit the potential of KNL for parallel graph processing

Yi-jay Lin - One of the best experts on this subject based on the ideXlab platform.

  • Generating efficient Local Memory Access sequences for coupled subscripts in data-parallel programs
    Information Sciences, 2003
    Co-Authors: Tsung-chuan Huang, Liang-cheng Shiu, Yi-jay Lin
    Abstract:

    Generating the Local Memory Access sequences is an integral part of compiling a data-parallel program into an SPMD code. Most previous research into Local Memory Access sequences have focused on one-dimensional arrays distributed with CYCLIC(k) distribution. The Local Memory Access sequences for multidimensional arrays with independent subscripts are produced by repeatedly applying the method for one-dimensional arrays. However, the task becomes highly complex when subscripts are coupled such that the subscripts in different dimensions depend on the same loop induction variables. This paper presents an efficient approach to computing the iterations executed on each processor by exploiting repetitive patterns in Memory Accesses. Smaller iteration tables than those of Ramanujam [Code generation for complex subscripts in data-parallel programs, in: Z. Li et al. (Eds.), Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, vol. 1366, Springer-Verlag, Berlin, 1998, pp. 49-63] are used, the iteration gap table is not required. The method has been implemented on an IBM SP2. Experimental results demonstrate the efficiency of the proposed method.

Tsung-chuan Huang - One of the best experts on this subject based on the ideXlab platform.

  • The Local Memory Access sequence of multiple induction variables on distributed Memory machines
    Computers & Electrical Engineering, 2004
    Co-Authors: Tsung-chuan Huang, Liang-cheng Shiu, Hwa-jyh Jean
    Abstract:

    Abstract Generating the Local Memory Access sequence is an important issue while compiling a data-parallel language into an SPMD code. There are many researches dealing with this issue for cyclic(k) distribution in simple subscripts. But the problem becomes highly complicated when the array references are with complex subscripts. One of the complex array reference functions is array subscript containing multiple induction variables (MIV subscripts). MIV is an affine combination of two or more nested loop indices in a single dimension. In this paper, we develop a general method in O(k) time to evaluate the start element for a given global start element. We compute the course distance first, and then traverse the FSM until the start element is found. In our method, the FSM table constructed in the one-level algorithm [J. Parallel Distr. Comput. 26(1) (1995) 72] can be used directly, but in the method of Ramanujam et al. [Languages and Compilers for Parallel Computing, vol. 1366. Springer-Verlag, 1998, p. 49] the l , r vectors of the processor must be evaluated for each global start element and the time-expensive operations like division and mod are required to check the space boundary of processors. Experimental results have revealed our method is more efficient than theirs.

  • Generating efficient Local Memory Access sequences for coupled subscripts in data-parallel programs
    Information Sciences, 2003
    Co-Authors: Tsung-chuan Huang, Liang-cheng Shiu, Yi-jay Lin
    Abstract:

    Generating the Local Memory Access sequences is an integral part of compiling a data-parallel program into an SPMD code. Most previous research into Local Memory Access sequences have focused on one-dimensional arrays distributed with CYCLIC(k) distribution. The Local Memory Access sequences for multidimensional arrays with independent subscripts are produced by repeatedly applying the method for one-dimensional arrays. However, the task becomes highly complex when subscripts are coupled such that the subscripts in different dimensions depend on the same loop induction variables. This paper presents an efficient approach to computing the iterations executed on each processor by exploiting repetitive patterns in Memory Accesses. Smaller iteration tables than those of Ramanujam [Code generation for complex subscripts in data-parallel programs, in: Z. Li et al. (Eds.), Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, vol. 1366, Springer-Verlag, Berlin, 1998, pp. 49-63] are used, the iteration gap table is not required. The method has been implemented on an IBM SP2. Experimental results demonstrate the efficiency of the proposed method.

Jiang Lei - One of the best experts on this subject based on the ideXlab platform.

  • Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture
    'Institute of Electrical and Electronics Engineers (IEEE)', 2019
    Co-Authors: Jiang Lei, Chen Langshi, Qiu Judy
    Abstract:

    Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. Among emerging killer applications, parallel graph processing has been a critical technique to analyze connected data. In this paper, we empirically evaluate various computing platforms including an Intel Xeon E5 CPU, a Nvidia Geforce GTX1070 GPU and an Xeon Phi 7210 processor codenamed Knights Landing (KNL) in the domain of parallel graph processing. We show that the KNL gains encouraging performance when processing graphs, so that it can become a promising solution to accelerating multi-threaded graph applications. We further characterize the impact of KNL architectural enhancements on the performance of a state-of-the art graph framework.We have four key observations: 1 Different graph applications require distinctive numbers of threads to reach the peak performance. For the same application, various datasets need even different numbers of threads to achieve the best performance. 2 Only a few graph applications benefit from the high bandwidth MCDRAM, while others favor the low latency DDR4 DRAM. 3 Vector processing units executing AVX512 SIMD instructions on KNLs are underutilized when running the state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering the lowest Local Memory Access latency hurts the performance of graph benchmarks that are lack of NUMA awareness. At last, We suggest future works including system auto-tuning tools and graph framework optimizations to fully exploit the potential of KNL for parallel graph processing.Comment: published as L. Jiang, L. Chen and J. Qiu, "Performance Characterization of Multi-threaded Graph Processing Applications on Many-Integrated-Core Architecture," 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, United Kingdom, 2018, pp. 199-20

  • Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture
    2019
    Co-Authors: Jiang Lei, Chen Langshi, Qiu Judy
    Abstract:

    Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of terascale integration. Among emerging killer applications, parallel graph processing has been a critical technique to analyze connected data. In this paper, we empirically evaluate various computing platforms including an Intel Xeon E5 CPU, a Nvidia Geforce GTX1070 GPU and an Xeon Phi 7210 processor codenamed Knights Landing (KNL) in the domain of parallel graph processing. We show that the KNL gains encouraging performance when processing graphs, so that it can become a promising solution to accelerating multi-threaded graph applications. We further characterize the impact of KNL architectural enhancements on the performance of a state-of-the art graph framework.We have four key observations: 1 Different graph applications require distinctive numbers of threads to reach the peak performance. For the same application, various datasets need even different numbers of threads to achieve the best performance. 2 Only a few graph applications benefit from the high bandwidth MCDRAM, while others favor the low latency DDR4 DRAM. 3 Vector processing units executing AVX512 SIMD instructions on KNLs are underutilized when running the state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering the lowest Local Memory Access latency hurts the performance of graph benchmarks that are lack of NUMA awareness. At last, We suggest future works including system auto-tuning tools and graph framework optimizations to fully exploit the potential of KNL for parallel graph processing

Liang-cheng Shiu - One of the best experts on this subject based on the ideXlab platform.

  • The Local Memory Access sequence of multiple induction variables on distributed Memory machines
    Computers & Electrical Engineering, 2004
    Co-Authors: Tsung-chuan Huang, Liang-cheng Shiu, Hwa-jyh Jean
    Abstract:

    Abstract Generating the Local Memory Access sequence is an important issue while compiling a data-parallel language into an SPMD code. There are many researches dealing with this issue for cyclic(k) distribution in simple subscripts. But the problem becomes highly complicated when the array references are with complex subscripts. One of the complex array reference functions is array subscript containing multiple induction variables (MIV subscripts). MIV is an affine combination of two or more nested loop indices in a single dimension. In this paper, we develop a general method in O(k) time to evaluate the start element for a given global start element. We compute the course distance first, and then traverse the FSM until the start element is found. In our method, the FSM table constructed in the one-level algorithm [J. Parallel Distr. Comput. 26(1) (1995) 72] can be used directly, but in the method of Ramanujam et al. [Languages and Compilers for Parallel Computing, vol. 1366. Springer-Verlag, 1998, p. 49] the l , r vectors of the processor must be evaluated for each global start element and the time-expensive operations like division and mod are required to check the space boundary of processors. Experimental results have revealed our method is more efficient than theirs.

  • Generating efficient Local Memory Access sequences for coupled subscripts in data-parallel programs
    Information Sciences, 2003
    Co-Authors: Tsung-chuan Huang, Liang-cheng Shiu, Yi-jay Lin
    Abstract:

    Generating the Local Memory Access sequences is an integral part of compiling a data-parallel program into an SPMD code. Most previous research into Local Memory Access sequences have focused on one-dimensional arrays distributed with CYCLIC(k) distribution. The Local Memory Access sequences for multidimensional arrays with independent subscripts are produced by repeatedly applying the method for one-dimensional arrays. However, the task becomes highly complex when subscripts are coupled such that the subscripts in different dimensions depend on the same loop induction variables. This paper presents an efficient approach to computing the iterations executed on each processor by exploiting repetitive patterns in Memory Accesses. Smaller iteration tables than those of Ramanujam [Code generation for complex subscripts in data-parallel programs, in: Z. Li et al. (Eds.), Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science, vol. 1366, Springer-Verlag, Berlin, 1998, pp. 49-63] are used, the iteration gap table is not required. The method has been implemented on an IBM SP2. Experimental results demonstrate the efficiency of the proposed method.