The Experts below are selected from a list of 279 Experts worldwide ranked by ideXlab platform
Robert A. Scholtz - One of the best experts on this subject based on the ideXlab platform.
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Analysis Of Noise In Optical Phase-Locked Loop
1993Co-Authors: Moe Z. Win, Chien C. Chen, Robert A. ScholtzAbstract:Report presents theoretical and experimental analysis of noise in coherent optical phase-Locked Loop. Optical phase-Locked Loop being considered for use in heterodyne reception of binary pulse-position modulation at data rate of 100 Kb/s in optical communication system in which transmitter also includes frequency-stabilized laser.
Duncan G. Elliott - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - An alias-Locked Loop frequency synthesis architecture
2008 IEEE International Symposium on Circuits and Systems, 2008Co-Authors: L. Van Den Berg, Duncan G. ElliottAbstract:This paper presents a phase-Locked Loop (PLL) using an aliasing divider, referred to as an alias-Locked Loop (ALL). The ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider in the feedback path. To examine the lock-in behaviour of the alias-Locked Loop, a nonlinear model is developed and used to simulate the architecture in the Locked state. Simulation results demonstrate the existence of stable modes of operation with bounded orbits. A version of the ALL is designed in 90-nm CMOS technology and simulated.
Taekwang Jang - One of the best experts on this subject based on the ideXlab platform.
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a reference oversampling digital phase Locked Loop with 240 db fom and 80 dbc reference spur
Symposium on VLSI Circuits, 2019Co-Authors: Jihwan Seol, Dennis Sylvester, David Blaauw, Taekwang JangAbstract:This paper proposes a reference oversampling phase-Locked Loop that simultaneously suppresses in-band noise and oscillator noise while maintaining a low reference spur. The proposed phase Locked Loop achieves -240.3 dB Figure of Merit (FOM) and -80 dBc reference spur. The integrated jitter is 508 fs$_{rms}$ and the power consumption is 3.6 mW at 2 GHz output clock frequency.
Liu Li-jing - One of the best experts on this subject based on the ideXlab platform.
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Design and Implementation of Pulse Sampling Phase-Locked Loop
Computer & Network, 2011Co-Authors: Liu Li-jingAbstract:To design pulse sampling phase—Locked Loop,this paper describes die basic operation principle,analyzes the model of phase noise and puts forward the problems in implementation.In die design,the high—frequency integrated sampling phase detector and DRO performance with lower phase noise,high spectral purity and high frequency stability are adopted.The simulation is implemented by ADS,and the simulation result shows that the higher specification of phase noise is realized.The result of phase noise of sampling phase—Locked Loop is similar to the theoretical value.Compared with numeral phase—Locked Loop,the pulse sampling phase-Locked Loop has excellent performance of phase noise.
Moe Z. Win - One of the best experts on this subject based on the ideXlab platform.
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Analysis Of Noise In Optical Phase-Locked Loop
1993Co-Authors: Moe Z. Win, Chien C. Chen, Robert A. ScholtzAbstract:Report presents theoretical and experimental analysis of noise in coherent optical phase-Locked Loop. Optical phase-Locked Loop being considered for use in heterodyne reception of binary pulse-position modulation at data rate of 100 Kb/s in optical communication system in which transmitter also includes frequency-stabilized laser.
