The Experts below are selected from a list of 14073 Experts worldwide ranked by ideXlab platform
Kazimierz Wiatr - One of the best experts on this subject based on the ideXlab platform.
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median and morphoLogical specialized Processors for a real time image data processing
EURASIP Journal on Advances in Signal Processing, 2002Co-Authors: Kazimierz WiatrAbstract:This paper presents the considerations on selecting a multiProcessor MISD architecture for fast implementation of the vision image processing. Using the author's earlier experience with real-time systems, implementing of specialized hardware Processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following Processors are presented: median filter and morphoLogical Processor. The structure of a universal reconfigurable Processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphoLogical Processor, convolution Processor, look-up-table Processor, Logic Processor and histogram Processor. These times compare with delays in general purpose Processor and DSP Processor.
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pipeline architecture of specialized reconfigurable Processors in fpga structures for real time image pre processing
Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204), 1998Co-Authors: Kazimierz WiatrAbstract:The article presents considerations concerning the choice of a multiProcessor unit architecture for fast realization of the tasks connected with initial processing of visual images. Based on the earlier experience of the author within the scope of real time systems, implementation in pipeline architecture of specialized hardware Processor-assembled on the basis of FPGA programmable structures-was suggested. In particular, implementation of the following Processor has been prepared: median filtration, convolution, look-up-table recording, Logic Processor, histogram count-up and morphoLogical Processors. Experimental work has also been done, in order to verify the concept assumed, whose results associated with delay times are included in the article. A structure of universal reconfigurable Processor has been moreover offered. The works have been financed by the Polish Scientific Research Committee.
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dedicated hardware Processors for a real time image data pre processing implemented in fpga structure
International Conference on Image Analysis and Processing, 1997Co-Authors: Kazimierz WiatrAbstract:This paper presents a dedicated hardware Processors implemented in FPGA structure for a fast video image data pre-processing to real time application. Author design and made specialised pipelined multiProcessor architecture for specialised hardware Processors. This paper presents specialised hardware Processors: median filter, Logic Processor, look-up-table Processor, convolution Processor and histogrammer. Dedicated hardware Processors implementation in the Xilinx FPGA used another chips. This work is supported by Polish Science Comitee.
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specialised architecture of dedicated hardware Processors for real time image data pre processing
Real-time Systems, 1997Co-Authors: Kazimierz WiatrAbstract:The conventional approach to video image processing is connected to many data transfers between video memory buffer and microProcessor units. Therefore, eliminating time consuming transfers and applying a pipelined image processing system seems to be a valuable solution. This architecture is particularly suitable for low level image processing. The author designed and built a specialised pipelined multiProcessor architecture for specialised hardware Processors. A special, custom pipeline bus standard was designed to provide a convincing way of applying pipeline Processors. The author designed and built some dedicated hardware Processors in FPGA structure: median filter, Logic Processor, look-up-table Processor, convolution Processor and histogrammer. Dedicated hardware Processor implementation in the Xilinx FPGA used other chips: FIFO buffers and Triple Port RAM.
Serge Weber - One of the best experts on this subject based on the ideXlab platform.
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Kalman filter and a fuzzy Logic Processor for series arcing fault detection in a home electrical network
International Journal of Electrical Power and Energy Systems, 2019Co-Authors: Edwin Calderon-mendoza, Patrick Schweitzer, Serge WeberAbstract:This paper presents a method for detecting series arcing faults in AC home electrical networks. The proposed algorithm is based on both a Kalman filter, used for identifying fault symptoms and a decision block, which confirms the presence of a series arc fault to activate a tripping signal. The current measured at one end of the power line is estimated using a model of two steady-state variables (X1 and X2). Firstly, residuals and the third order difference of state X2 are used as input parameters of a Fuzzy Logic Processor for detecting fault symptoms. Secondly, the fault symptoms are processed by a detection Logic block, which confirms the presence of an electrical arcing fault. The algorithm is tested on a variety of loads in single or masking load configurations chosen accordingly to the requirements of the UL 1699 and IEC 62606 standards. The algorithm is also tested in the steady state or at load start (transient state). This method's performance is studied and discussed in the final part. Experimental results show that the method we propose can detect arcing faults efficiently, avoiding false tripping, whilst taking into account a high degree of diagnosis accuracy and average detection time.
Edwin Calderon-mendoza - One of the best experts on this subject based on the ideXlab platform.
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Kalman filter and a fuzzy Logic Processor for series arcing fault detection in a home electrical network
International Journal of Electrical Power and Energy Systems, 2019Co-Authors: Edwin Calderon-mendoza, Patrick Schweitzer, Serge WeberAbstract:This paper presents a method for detecting series arcing faults in AC home electrical networks. The proposed algorithm is based on both a Kalman filter, used for identifying fault symptoms and a decision block, which confirms the presence of a series arc fault to activate a tripping signal. The current measured at one end of the power line is estimated using a model of two steady-state variables (X1 and X2). Firstly, residuals and the third order difference of state X2 are used as input parameters of a Fuzzy Logic Processor for detecting fault symptoms. Secondly, the fault symptoms are processed by a detection Logic block, which confirms the presence of an electrical arcing fault. The algorithm is tested on a variety of loads in single or masking load configurations chosen accordingly to the requirements of the UL 1699 and IEC 62606 standards. The algorithm is also tested in the steady state or at load start (transient state). This method's performance is studied and discussed in the final part. Experimental results show that the method we propose can detect arcing faults efficiently, avoiding false tripping, whilst taking into account a high degree of diagnosis accuracy and average detection time.
Patrick Schweitzer - One of the best experts on this subject based on the ideXlab platform.
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Kalman filter and a fuzzy Logic Processor for series arcing fault detection in a home electrical network
International Journal of Electrical Power and Energy Systems, 2019Co-Authors: Edwin Calderon-mendoza, Patrick Schweitzer, Serge WeberAbstract:This paper presents a method for detecting series arcing faults in AC home electrical networks. The proposed algorithm is based on both a Kalman filter, used for identifying fault symptoms and a decision block, which confirms the presence of a series arc fault to activate a tripping signal. The current measured at one end of the power line is estimated using a model of two steady-state variables (X1 and X2). Firstly, residuals and the third order difference of state X2 are used as input parameters of a Fuzzy Logic Processor for detecting fault symptoms. Secondly, the fault symptoms are processed by a detection Logic block, which confirms the presence of an electrical arcing fault. The algorithm is tested on a variety of loads in single or masking load configurations chosen accordingly to the requirements of the UL 1699 and IEC 62606 standards. The algorithm is also tested in the steady state or at load start (transient state). This method's performance is studied and discussed in the final part. Experimental results show that the method we propose can detect arcing faults efficiently, avoiding false tripping, whilst taking into account a high degree of diagnosis accuracy and average detection time.
Changwook Han - One of the best experts on this subject based on the ideXlab platform.
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evolutionary optimization of union based rule antecedent fuzzy neural networks and its applications
Intelligent Data Engineering and Automated Learning, 2008Co-Authors: Changwook HanAbstract:A union-based rule-antecedent fuzzy neural networks (URFNN), which can guarantee a parsimonious knowledge base with reduced number of rules, is proposed. The URFNN allows union operation of input fuzzy sets in the antecedents to cover bigger input domain compared with the complete structure rule which consists of AND combination of all input variables in its premise. To construct the URFNN, we consider the union-based Logic Processor (ULP) which consists of OR and AND fuzzy neurons. The fuzzy neurons exhibit learning abilities as they come with a collection of adjustable connection weights. In the development stage, genetic algorithm (GA) constructs a Boolean skeleton of URFNN, while gradient-based learning refines the binary connections of GA-optimized URFNN for further improvement of the performance index. A cart-pole system is considered to verify the effectiveness of the proposed method.
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designing a self adaptive union based rule antecedent fuzzy controller based on two step optimization
International Conference on Knowledge-Based and Intelligent Information and Engineering Systems, 2006Co-Authors: Changwook Han, Jungil ParkAbstract:A self-adaptive union-based rule-antecedent fuzzy controller (SURFCon), which can guarantee a parsimonious knowledge base with reduced number of rules, is proposed. The SURFCon allows union operation of input fuzzy sets in the antecedents to cover bigger input domain compared with the complete structure rule which consists of AND combination of all input variables in its premise. To construct the SURFCon, we consider the union-based Logic Processor (ULP) which consists of OR and AND fuzzy neurons. The fuzzy neurons exhibit learning abilities as they come with a collection of adjustable connection weights. In the development stage, genetic algorithm (GA) constructs a Boolean skeleton of SURFCon, while stochastic reinforcement learning refines the binary connections of GA-optimized SURFCon for further improvement of the performance index. A cart-pole system is considered to verify the effectiveness of the proposed method.
