The Experts below are selected from a list of 36 Experts worldwide ranked by ideXlab platform
Romanovskiy Vladimir - One of the best experts on this subject based on the ideXlab platform.
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Integrating LHCb workflows on HPC resources: status and strategies
'EDP Sciences', 2020Co-Authors: Stagni Federico, Valassi Andrea, Romanovskiy VladimirAbstract:High Performance Computing (HPC) supercomputers are expected to play an increasingly important role in HEP computing in the coming years. While HPC resources are not necessarily the optimal fit for HEP workflows, computing time at HPC centers on an opportunistic basis has already been available to the LHC experiments for some time, and it is also possible that part of the pledged computing resources will be offered as CPU time allocations at HPC centers in the future. The integration of the experiment workflows to make the most efficient use of HPC resources is therefore essential. This paper describes the work that has been necessary to integrate LHCb workflows at a specific HPC site, the Marconi-A2 system at CINECA in Italy, where LHCb benefited from a joint PRACE (Partnership for Advanced Computing in Europe) allocation with the other Large Hadron Collider (LHC) experiments. This has required addressing two types of challenges: on the software application workloads, for optimising their performance on a many-core hardware architecture that differs significantly from those traditionally used in WLCG (Worldwide LHC Computing Grid), by reducing memory footprint using a multi-process approach; and in the distributed computing area, for submitting these workloads using more than one Logical Processor per job, which had never been done yet in LHCb
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Integrating LHCb workflows on HPC resources: status and strategies
'EDP Sciences', 2020Co-Authors: Stagni Federico, Valassi Andrea, Romanovskiy VladimirAbstract:High Performance Computing (HPC) supercomputers are expected to play an increasingly important role in HEP computing in the coming years. While HPC resources are not necessarily the optimal fit for HEP workflows, computing time at HPC centers on an opportunistic basis has already been available to the LHC experiments for some time, and it is also possible that part of the pledged computing resources will be offered as CPU time allocations at HPC centers in the future. The integration of the experiment workflows to make the most efficient use of HPC resources is therefore essential. This paper describes the work that has been necessary to integrate LHCb workflows at a specific HPC site, the Marconi-A2 system at CINECA in Italy, where LHCb benefited from a joint PRACE (Partnership for Advanced Computing in Europe) allocation with the other Large Hadron Collider (LHC) experiments. This has required addressing two types of challenges: on the software application workloads, for optimising their performance on a many-core hardware architecture that differs significantly from those traditionally used in WLCG (Worldwide LHC Computing Grid), by reducing memory footprint using a multi-process approach; and in the distributed computing area, for submitting these workloads using more than one Logical Processor per job, which had never been done yet in LHCb.Comment: 9 pages, submitted to CHEP2019 proceedings in EPJ Web of Conference
Mohammad A. Karim - One of the best experts on this subject based on the ideXlab platform.
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Multioutput Logical Processor using joint transform correlator
Microwave and Optical Technology Letters, 1994Co-Authors: Mohammad S. Alam, Mohammad A. KarimAbstract:Joint transform correlation is applied for real-time optical implementation of Logical Processor. As an example, a 4–to–2 line encoder is considered. Simulation results for both sequential and parallel implementation techniques are presented. © 1994 John Wiley & Sons, Inc.
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Joint transform correlator based Logical Processor
Proceedings of the IEEE 1992 National Aerospace and Electronics Conference@m_NAECON 1992, 1Co-Authors: Mohammad S. Alam, Mohammad A. KarimAbstract:Real-time optical implementation of a Logical Processor using a joint transform correlator (JTC) is proposed. For illustration, the authors implemented a 4-to-2 encoder using a JTC by spatially encoding the corresponding minterms. Since the use of a single JTC may slow down a logic system with a large number of minterms, a multichannel JTC (MJTC) may be used to speed up the processing. For the MJTC, it was found that four-minterm-based reference images can be used in each channel without significantly deteriorating the system efficiency. Simulation results for both sequential and parallel implementation techniques are presented. >
Stagni Federico - One of the best experts on this subject based on the ideXlab platform.
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Integrating LHCb workflows on HPC resources: status and strategies
'EDP Sciences', 2020Co-Authors: Stagni Federico, Valassi Andrea, Romanovskiy VladimirAbstract:High Performance Computing (HPC) supercomputers are expected to play an increasingly important role in HEP computing in the coming years. While HPC resources are not necessarily the optimal fit for HEP workflows, computing time at HPC centers on an opportunistic basis has already been available to the LHC experiments for some time, and it is also possible that part of the pledged computing resources will be offered as CPU time allocations at HPC centers in the future. The integration of the experiment workflows to make the most efficient use of HPC resources is therefore essential. This paper describes the work that has been necessary to integrate LHCb workflows at a specific HPC site, the Marconi-A2 system at CINECA in Italy, where LHCb benefited from a joint PRACE (Partnership for Advanced Computing in Europe) allocation with the other Large Hadron Collider (LHC) experiments. This has required addressing two types of challenges: on the software application workloads, for optimising their performance on a many-core hardware architecture that differs significantly from those traditionally used in WLCG (Worldwide LHC Computing Grid), by reducing memory footprint using a multi-process approach; and in the distributed computing area, for submitting these workloads using more than one Logical Processor per job, which had never been done yet in LHCb
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Integrating LHCb workflows on HPC resources: status and strategies
'EDP Sciences', 2020Co-Authors: Stagni Federico, Valassi Andrea, Romanovskiy VladimirAbstract:High Performance Computing (HPC) supercomputers are expected to play an increasingly important role in HEP computing in the coming years. While HPC resources are not necessarily the optimal fit for HEP workflows, computing time at HPC centers on an opportunistic basis has already been available to the LHC experiments for some time, and it is also possible that part of the pledged computing resources will be offered as CPU time allocations at HPC centers in the future. The integration of the experiment workflows to make the most efficient use of HPC resources is therefore essential. This paper describes the work that has been necessary to integrate LHCb workflows at a specific HPC site, the Marconi-A2 system at CINECA in Italy, where LHCb benefited from a joint PRACE (Partnership for Advanced Computing in Europe) allocation with the other Large Hadron Collider (LHC) experiments. This has required addressing two types of challenges: on the software application workloads, for optimising their performance on a many-core hardware architecture that differs significantly from those traditionally used in WLCG (Worldwide LHC Computing Grid), by reducing memory footprint using a multi-process approach; and in the distributed computing area, for submitting these workloads using more than one Logical Processor per job, which had never been done yet in LHCb.Comment: 9 pages, submitted to CHEP2019 proceedings in EPJ Web of Conference
Mohammad S. Alam - One of the best experts on this subject based on the ideXlab platform.
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Multioutput Logical Processor using joint transform correlator
Microwave and Optical Technology Letters, 1994Co-Authors: Mohammad S. Alam, Mohammad A. KarimAbstract:Joint transform correlation is applied for real-time optical implementation of Logical Processor. As an example, a 4–to–2 line encoder is considered. Simulation results for both sequential and parallel implementation techniques are presented. © 1994 John Wiley & Sons, Inc.
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Joint transform correlator based Logical Processor
Proceedings of the IEEE 1992 National Aerospace and Electronics Conference@m_NAECON 1992, 1Co-Authors: Mohammad S. Alam, Mohammad A. KarimAbstract:Real-time optical implementation of a Logical Processor using a joint transform correlator (JTC) is proposed. For illustration, the authors implemented a 4-to-2 encoder using a JTC by spatially encoding the corresponding minterms. Since the use of a single JTC may slow down a logic system with a large number of minterms, a multichannel JTC (MJTC) may be used to speed up the processing. For the MJTC, it was found that four-minterm-based reference images can be used in each channel without significantly deteriorating the system efficiency. Simulation results for both sequential and parallel implementation techniques are presented. >
T. Kubo - One of the best experts on this subject based on the ideXlab platform.
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COMPSAC (1) - New method for dispatching waiting Logical Processors in virtual machine system
29th Annual International Computer Software and Applications Conference (COMPSAC'05), 1Co-Authors: H. Umeno, M. Kiyama, T. Fukunaga, T. KuboAbstract:A virtual machine system can run multiple conventional operating systems (OSs) in a single real host computer. A virtual machine is a Logical computer with almost the same architecture as the host, and may contain several Logical Processors. A hypervisor is a control program to control this virtual machine system. Traditionally, the hypervisor has to receive an I/O interrupt pending for a waiting Logical Processor, and to simulate the I/O interrupt, consequently incurring the simulation overhead of the I/O interrupt. To avoid this overhead we present a new method which introduces a new self-wait state different from the conventional wait state, presents a new instruction for the hypervisor to detect the I/O interrupts pending for the Logical Processors in the self-wait state, and dispatches those Logical Processors on the detection ahead of the ready queue. This new method has eliminated the simulation overhead of those I/O interrupts, and enhanced the system performance to the near native.
