The Experts below are selected from a list of 255 Experts worldwide ranked by ideXlab platform
Un-ku Moon - One of the best experts on this subject based on the ideXlab platform.
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a sub picosecond resolution 0 5 1 5 ghz digital to Phase converter
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Pavan Kumar Hanumolu, V Kratyuk, Guyeon Wei, Un-ku MoonAbstract:A digital-to-Phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital Phase modulators. The resolution of DPCs using analog Phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 Phases generated by a Phase-locked Loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked Loop Phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.
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Analysis of charge-pump Phase-locked Loops
IEEE Transactions on Circuits and Systems I: Regular Papers, 2004Co-Authors: Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-ku MoonAbstract:In this paper, we present an exact analysis for third-order charge-pump Phase-locked Loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the Loop parameters and the reference frequency on the Loop Phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.
Zhihua Wang - One of the best experts on this subject based on the ideXlab platform.
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a 10 b fourth order quadrature bandpass continuous time sigma delta modulator with 33 mhz bandwidth for a dual channel gnss receiver
IEEE Transactions on Microwave Theory and Techniques, 2017Co-Authors: Junfeng Zhang, Yang Xu, Zehong Zhang, Zhihua WangAbstract:A fourth-order quadrature bandpass continuous-time sigma–delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the Loop-stability of the high-order architecture, any extra Loop Phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order Loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess Loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital–analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.
Pavan Kumar Hanumolu - One of the best experts on this subject based on the ideXlab platform.
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a sub picosecond resolution 0 5 1 5 ghz digital to Phase converter
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Pavan Kumar Hanumolu, V Kratyuk, Guyeon Wei, Un-ku MoonAbstract:A digital-to-Phase converter (DPC) is an essential building block in applications such as source-synchronous interfaces and digital Phase modulators. The resolution of DPCs using analog Phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 Phases generated by a Phase-locked Loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked Loop Phase filter. The test chip, fabricated in a 0.13 mum CMOS process, operates from 0.5 -1.5 GHz and achieves a differential nonlinearity of less than plusmn0.1 ps and an integral nonlinearity of plusmn12 ps. The total power consumption while operating at 1 GHz is 15 mW.
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Analysis of charge-pump Phase-locked Loops
IEEE Transactions on Circuits and Systems I: Regular Papers, 2004Co-Authors: Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-ku MoonAbstract:In this paper, we present an exact analysis for third-order charge-pump Phase-locked Loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the Loop parameters and the reference frequency on the Loop Phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.
Junfeng Zhang - One of the best experts on this subject based on the ideXlab platform.
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a 10 b fourth order quadrature bandpass continuous time sigma delta modulator with 33 mhz bandwidth for a dual channel gnss receiver
IEEE Transactions on Microwave Theory and Techniques, 2017Co-Authors: Junfeng Zhang, Yang Xu, Zehong Zhang, Zhihua WangAbstract:A fourth-order quadrature bandpass continuous-time sigma–delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the Loop-stability of the high-order architecture, any extra Loop Phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order Loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess Loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital–analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.
Nils Pohl - One of the best experts on this subject based on the ideXlab platform.
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versatile dual receiver 94 ghz fmcw radar system with high output power and 26 ghz tuning range for high distance applications
IEEE Transactions on Microwave Theory and Techniques, 2020Co-Authors: Benedikt Welp, Steffen Hansen, Gunnar Briese, Simon Kuppers, Sven Thomas, Christian Bredendiek, Nils PohlAbstract:Airborne applications demand exceptional overall radar system performance and eminently high output power for high range target detection. The frequency modulated continuous wave (FMCW) radar system presented in this article is capable of achieving this task due to its high output power at 94-GHz center frequency with over 26-GHz tuning range. Nevertheless, the radar still provides a small form factor and low power consumption of 4.25 W at 5 V single Universal Serial Bus (USB) supply. The key system component is a Silicon Germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) monolithic microwave integrated circuit (MMIC) that contains a 94-GHz voltage-controlled oscillator (VCO), and a 27-GHz VCO for dual-Loop Phase-locked Loop (PLL) stabilization, a power amplifier (PA), and two receive mixers. It generates frequency ramps between 83- and 109-GHz with a maximum output power of 19.7 dBm at its output after the bond wires on the printed circuit board (PCB) and 14.8-dBm output power at the radar’s transmit (TX)-waveguide WR-10-flange. The sensor was also tested in a temperature range from −40 °C to +70 °C with menial deviation. Thus, the system offers high system dynamic range and far distance target detection range. Following a detailed system description, we finally present the FMCW range and Doppler measurements performed with the presented radar sensor as well as the application on unmanned aerial vehicles (UAVs) for flight altitude control and as airborne collision avoidance system (ACAS).
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an ultra wideband 80 ghz fmcw radar system using a sige bipolar transceiver chip stabilized by a fractional n pll synthesizer
IEEE Transactions on Microwave Theory and Techniques, 2012Co-Authors: Nils Pohl, Timo Jaeschke, Klaus AufingerAbstract:A radar system with an ultra-wide FMCW ramp bandwidth of 25.6 GHz (≈32%) around a center frequency of 80 GHz is presented. The system is based on a monostatic fully integrated SiGe transceiver chip, which is stabilized using conventional fractional-N PLL chips at a reference frequency of 100 MHz. The achieved in-Loop Phase noise is ≈ -88 dBc/Hz (10 kHz offset frequency) for the center frequency and below ≈-80 dBc/Hz in the wide frequency band of 25.6 GHz for all offset frequencies >;1 kHz. The ultra-wide PLL-stabilization was achieved using a reverse frequency position mixer in the PLL (offset-PLL) resulting in a compensation of the variation of the oscillators tuning sensitivity with the variation of the N-divider in the PLL. The output power of the transceiver chip, as well as of the mm-wave module (containing a waveguide transition), is sufficiently flat versus the output frequency (variation <;3 dB). In radar measurements using the full bandwidth an ultra-high spatial resolution of 7.12 mm was achieved. The standard deviation between repeated measurements of the same target is 0.36 μm.
