The Experts below are selected from a list of 42 Experts worldwide ranked by ideXlab platform
Ming-yung Ko - One of the best experts on this subject based on the ideXlab platform.
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Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation
IEEE Transactions on Signal Processing, 2007Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. DeprettereAbstract:In this paper, we present a technique for compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression
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ASAP - Parameterized Looped Schedules for Compact Representationof Execution Sequences
IEEE 17th International Conference on Application-specific Systems Architectures and Processors (ASAP'06), 2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian PuthenpurayilAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many DSP system synthesis contexts, including efficient control generation for Kahn processes on FPGAs, and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression. In our experiments, this new approach demonstrates up to 99% storage saving (versus RLE) and up to 46% frequency enhancement (versus another parameterized approach) in FPGA synthesis, and an average of 11% code size reduction in software synthesis compared to existing methods for code size reduction.
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Parameterized Looped Schedules
2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Rami Nasr, Bart Kienhius, Ed F. DeprettereAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct we mean a compact way of specifying a finite repetition of a set of execution primitives (“instructions”). Such compaction, which can be viewed as a form of hierarchical run-length encoding, has application in many embedded software contexts, including efficient control generation for Kahn processes [6], and software synthesis for static dataflow models of computation, such as synchronous dataflow [1] and cyclo-static dataflow [3]. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low overhead decompression.
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Parameterized Looped Schedules for Compact Representationof Execution Sequences
IEEE 17th International Conference on Application-specific Systems Architectures and Processors (ASAP'06), 2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian PuthenpurayilAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many DSP system synthesis contexts, including efficient control generation for Kahn processes on FPGAs, and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression. In our experiments, this new approach demonstrates up to 99% storage saving (versus RLE) and up to 46% frequency enhancement (versus another parameterized approach) in FPGA synthesis, and an average of 11% code size reduction in software synthesis compared to existing methods for code size reduction.
Sebastian Puthenpurayil - One of the best experts on this subject based on the ideXlab platform.
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Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation
IEEE Transactions on Signal Processing, 2007Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. DeprettereAbstract:In this paper, we present a technique for compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression
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ASAP - Parameterized Looped Schedules for Compact Representationof Execution Sequences
IEEE 17th International Conference on Application-specific Systems Architectures and Processors (ASAP'06), 2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian PuthenpurayilAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many DSP system synthesis contexts, including efficient control generation for Kahn processes on FPGAs, and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression. In our experiments, this new approach demonstrates up to 99% storage saving (versus RLE) and up to 46% frequency enhancement (versus another parameterized approach) in FPGA synthesis, and an average of 11% code size reduction in software synthesis compared to existing methods for code size reduction.
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Parameterized Looped Schedules
2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Rami Nasr, Bart Kienhius, Ed F. DeprettereAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct we mean a compact way of specifying a finite repetition of a set of execution primitives (“instructions”). Such compaction, which can be viewed as a form of hierarchical run-length encoding, has application in many embedded software contexts, including efficient control generation for Kahn processes [6], and software synthesis for static dataflow models of computation, such as synchronous dataflow [1] and cyclo-static dataflow [3]. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low overhead decompression.
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Parameterized Looped Schedules for Compact Representationof Execution Sequences
IEEE 17th International Conference on Application-specific Systems Architectures and Processors (ASAP'06), 2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian PuthenpurayilAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many DSP system synthesis contexts, including efficient control generation for Kahn processes on FPGAs, and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression. In our experiments, this new approach demonstrates up to 99% storage saving (versus RLE) and up to 46% frequency enhancement (versus another parameterized approach) in FPGA synthesis, and an average of 11% code size reduction in software synthesis compared to existing methods for code size reduction.
Ed F. Deprettere - One of the best experts on this subject based on the ideXlab platform.
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Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation
IEEE Transactions on Signal Processing, 2007Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. DeprettereAbstract:In this paper, we present a technique for compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression
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Parameterized Looped Schedules
2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Rami Nasr, Bart Kienhius, Ed F. DeprettereAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct we mean a compact way of specifying a finite repetition of a set of execution primitives (“instructions”). Such compaction, which can be viewed as a form of hierarchical run-length encoding, has application in many embedded software contexts, including efficient control generation for Kahn processes [6], and software synthesis for static dataflow models of computation, such as synchronous dataflow [1] and cyclo-static dataflow [3]. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low overhead decompression.
Claudiu Zissulescu - One of the best experts on this subject based on the ideXlab platform.
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Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation
IEEE Transactions on Signal Processing, 2007Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. DeprettereAbstract:In this paper, we present a technique for compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression
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ASAP - Parameterized Looped Schedules for Compact Representationof Execution Sequences
IEEE 17th International Conference on Application-specific Systems Architectures and Processors (ASAP'06), 2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian PuthenpurayilAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many DSP system synthesis contexts, including efficient control generation for Kahn processes on FPGAs, and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression. In our experiments, this new approach demonstrates up to 99% storage saving (versus RLE) and up to 46% frequency enhancement (versus another parameterized approach) in FPGA synthesis, and an average of 11% code size reduction in software synthesis compared to existing methods for code size reduction.
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Parameterized Looped Schedules
2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Rami Nasr, Bart Kienhius, Ed F. DeprettereAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct we mean a compact way of specifying a finite repetition of a set of execution primitives (“instructions”). Such compaction, which can be viewed as a form of hierarchical run-length encoding, has application in many embedded software contexts, including efficient control generation for Kahn processes [6], and software synthesis for static dataflow models of computation, such as synchronous dataflow [1] and cyclo-static dataflow [3]. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low overhead decompression.
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Parameterized Looped Schedules for Compact Representationof Execution Sequences
IEEE 17th International Conference on Application-specific Systems Architectures and Processors (ASAP'06), 2006Co-Authors: Ming-yung Ko, Claudiu Zissulescu, Sebastian PuthenpurayilAbstract:This paper is concerned with the compact representation of execution sequences in terms of efficient Looping Constructs. Here, by a Looping Construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many DSP system synthesis contexts, including efficient control generation for Kahn processes on FPGAs, and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of DSP programs to yield a configurable code compression methodology that exhibits a broad range of achievable trade-offs. Specifically, we formally develop and apply to DSP hardware and software implementation a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression. In our experiments, this new approach demonstrates up to 99% storage saving (versus RLE) and up to 46% frequency enhancement (versus another parameterized approach) in FPGA synthesis, and an average of 11% code size reduction in software synthesis compared to existing methods for code size reduction.
Malacariapasquale - One of the best experts on this subject based on the ideXlab platform.
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A static analysis for quantifying information flow in a simple imperative language
Journal of Computer Security, 2007Co-Authors: Clarkdavid, Huntsebastian, MalacariapasqualeAbstract:We propose an approach to quantify interference in a simple imperative language that includes a Looping Construct. In this paper we focus on a particular case of this definition of interference: le...
