The Experts below are selected from a list of 29973 Experts worldwide ranked by ideXlab platform
Vijay Raghunathan - One of the best experts on this subject based on the ideXlab platform.
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Spi-Snooper: A Hardware-Software Approach for Transparent Network Monitoring inWireless Sensor Networks
2015Co-Authors: Mohammad Sajjad Hossain, Woo Suk Lee, Vijay RaghunathanAbstract:The lack of post-deployment visibility into system operation is one of the major challenges in ensuring reliable operation of remotely-deployed embedded systems such as wireless sensor nodes. Over the years, many software-based solutions (in the form of debug-ging tools and protocols) have been proposed for in-situ system monitoring. However, all of them share the trait that the monitor-ing functionality is implemented as software executing on the same embedded Processor that the Main application executes on. This is a poor design choice from a reliability perspective. This paper makes the case for a joint hardware-software solution to this prob-lem and advocates the use of a dedicated reliability co-Processor that is tasked with monitoring the operation of the embedded sys-tem. As an embodiment of this design principle, this paper presents Spi-Snooper, a co-Processor augmented hardware platform specifi-cally designed for network monitoring. Spi-Snooper is completely cross-compatible with the Telos wireless sensor nodes from an op-erational standpoint and is based on a novel hardware architecture that enables transparent snooping of the communication bus be-tween the Main Processor and the radio of the wireless embed-ded system. The accompanying software architecture provides a powerful tool for monitoring, logging, and even controlling all the communication that takes place between the Main Processor and the radio. We present a rigorous evaluation of our prototype and demonstrate its utility using a variety of usage scenarios
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spi snooper a hardware software approach for transparent network monitoring in wireless sensor networks
International Conference on Hardware Software Codesign and System Synthesis, 2012Co-Authors: Mohammad Sajjad Hossain, Vijay RaghunathanAbstract:The lack of post-deployment visibility into system operation is one of the major challenges in ensuring reliable operation of remotely deployed embedded systems such as wireless sensor nodes. Over the years, many software-based solutions (in the form of debugging tools and protocols) have been proposed for in-situ system monitoring. However, all of them share the trait that the monitoring functionality is implemented as software executing on the same embedded Processor that the Main application executes on. This is a poor design choice from a reliability perspective. This paper makes the case for a joint hardware-software solution to this problem and advocates the use of a dedicated reliability co-Processor that is tasked with monitoring the operation of the embedded system. As an embodiment of this design principle, this paper presents Spi-Snooper, a co-Processor augmented hardware platform specifically designed for network monitoring. Spi-Snooper is completely cross-compatible with the Telos wireless sensor nodes from an operational standpoint and is based on a novel hardware architecture that enables transparent snooping of the communication bus between the Main Processor and the radio of the wireless embedded system. The accompanying software architecture provides a powerful tool for monitoring, logging, and even controlling all the communication that takes place between the Main Processor and the radio. We present a rigorous evaluation of our prototype and demonstrate its utility using a variety of usage scenarios.
Hoijun Yoo - One of the best experts on this subject based on the ideXlab platform.
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a 125 gops 583 mw network on chip based parallel Processor with bio inspired visual attention engine
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Kwanho Kim, Seungjin Lee, Jooyoung Kim, Minsu Kim, Hoijun YooAbstract:A network-on-chip (NoC) based parallel Processor is presented for bio-inspired real-time object recognition with visual attention algorithm. It contains an ARM10-compatible 32-bit Main Processor, 8 single-instruction multiple-data (SIMD) clusters with 8 processing elements in each cluster, a cellular neural network based visual attention engine (VAE), a matching accelerator, and a DMA-like external interface. The VAE with 2-D shift register array finds salient objects on the entire image rapidly. Then, the parallel Processor performs further detailed image processing within only the pre-selected attention regions. The low-latency NoC employs dual channel, adaptive switching and packet-based power management, providing 76.8 GB/s aggregated bandwidth. The 36 mm2 chip contains 1.9 M gates and 226 kB SRAM in a 0.13 mum 8-metal CMOS technology. The fabricated chip achieves a peak performance of 125 GOPS and 22 frames/sec object recognition while dissipating 583 mW at 1.2 V.
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a 125gops 583mw network on chip based parallel Processor with bio inspired visual attention engine
International Solid-State Circuits Conference, 2008Co-Authors: Kwanho Kim, Seungjin Lee, Jooyoung Kim, Minsu Kim, Donghyun Kim, Jeongho Woo, Hoijun YooAbstract:A network-on-chip (NoC) is applied to achieve extensive communication bandwidth required for parallel computing. A 125 GOPS NoC-based parallel Processor with a bio-inspired visual attention engine (VAE) exploits both data and object-level parallelism while dissipating 583 mW by packet-based power management. The use of more PEs, VAE, and low latency NoC enables higher performance and power efficiency over the previous design. NoC-based parallel Processor consisting of 12 IPs: a Main Processor, 8 PE clusters (PECs), VAE, a matching accelerator (MA), and an external interface. The ARMlO-compatible 32b Main Processor controls the overall system operations. The VAE detects the feature points on the entire image by neural network algorithms like contour extraction. The 8 PECs perform data-intensive image processing applications such as filtering and histogram calculations. The MA accelerates nearest neighbor search to obtain a final recognition result in real-time. The DMA-like external interface distributes automatically the corresponding image data to each PEC to reduce system overhead. Each core is connected to the NoC via a network interface.
Mohammad Sajjad Hossain - One of the best experts on this subject based on the ideXlab platform.
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Spi-Snooper: A Hardware-Software Approach for Transparent Network Monitoring inWireless Sensor Networks
2015Co-Authors: Mohammad Sajjad Hossain, Woo Suk Lee, Vijay RaghunathanAbstract:The lack of post-deployment visibility into system operation is one of the major challenges in ensuring reliable operation of remotely-deployed embedded systems such as wireless sensor nodes. Over the years, many software-based solutions (in the form of debug-ging tools and protocols) have been proposed for in-situ system monitoring. However, all of them share the trait that the monitor-ing functionality is implemented as software executing on the same embedded Processor that the Main application executes on. This is a poor design choice from a reliability perspective. This paper makes the case for a joint hardware-software solution to this prob-lem and advocates the use of a dedicated reliability co-Processor that is tasked with monitoring the operation of the embedded sys-tem. As an embodiment of this design principle, this paper presents Spi-Snooper, a co-Processor augmented hardware platform specifi-cally designed for network monitoring. Spi-Snooper is completely cross-compatible with the Telos wireless sensor nodes from an op-erational standpoint and is based on a novel hardware architecture that enables transparent snooping of the communication bus be-tween the Main Processor and the radio of the wireless embed-ded system. The accompanying software architecture provides a powerful tool for monitoring, logging, and even controlling all the communication that takes place between the Main Processor and the radio. We present a rigorous evaluation of our prototype and demonstrate its utility using a variety of usage scenarios
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spi snooper a hardware software approach for transparent network monitoring in wireless sensor networks
International Conference on Hardware Software Codesign and System Synthesis, 2012Co-Authors: Mohammad Sajjad Hossain, Vijay RaghunathanAbstract:The lack of post-deployment visibility into system operation is one of the major challenges in ensuring reliable operation of remotely deployed embedded systems such as wireless sensor nodes. Over the years, many software-based solutions (in the form of debugging tools and protocols) have been proposed for in-situ system monitoring. However, all of them share the trait that the monitoring functionality is implemented as software executing on the same embedded Processor that the Main application executes on. This is a poor design choice from a reliability perspective. This paper makes the case for a joint hardware-software solution to this problem and advocates the use of a dedicated reliability co-Processor that is tasked with monitoring the operation of the embedded system. As an embodiment of this design principle, this paper presents Spi-Snooper, a co-Processor augmented hardware platform specifically designed for network monitoring. Spi-Snooper is completely cross-compatible with the Telos wireless sensor nodes from an operational standpoint and is based on a novel hardware architecture that enables transparent snooping of the communication bus between the Main Processor and the radio of the wireless embedded system. The accompanying software architecture provides a powerful tool for monitoring, logging, and even controlling all the communication that takes place between the Main Processor and the radio. We present a rigorous evaluation of our prototype and demonstrate its utility using a variety of usage scenarios.
Kwanho Kim - One of the best experts on this subject based on the ideXlab platform.
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a 125 gops 583 mw network on chip based parallel Processor with bio inspired visual attention engine
IEEE Journal of Solid-state Circuits, 2009Co-Authors: Kwanho Kim, Seungjin Lee, Jooyoung Kim, Minsu Kim, Hoijun YooAbstract:A network-on-chip (NoC) based parallel Processor is presented for bio-inspired real-time object recognition with visual attention algorithm. It contains an ARM10-compatible 32-bit Main Processor, 8 single-instruction multiple-data (SIMD) clusters with 8 processing elements in each cluster, a cellular neural network based visual attention engine (VAE), a matching accelerator, and a DMA-like external interface. The VAE with 2-D shift register array finds salient objects on the entire image rapidly. Then, the parallel Processor performs further detailed image processing within only the pre-selected attention regions. The low-latency NoC employs dual channel, adaptive switching and packet-based power management, providing 76.8 GB/s aggregated bandwidth. The 36 mm2 chip contains 1.9 M gates and 226 kB SRAM in a 0.13 mum 8-metal CMOS technology. The fabricated chip achieves a peak performance of 125 GOPS and 22 frames/sec object recognition while dissipating 583 mW at 1.2 V.
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a 125gops 583mw network on chip based parallel Processor with bio inspired visual attention engine
International Solid-State Circuits Conference, 2008Co-Authors: Kwanho Kim, Seungjin Lee, Jooyoung Kim, Minsu Kim, Donghyun Kim, Jeongho Woo, Hoijun YooAbstract:A network-on-chip (NoC) is applied to achieve extensive communication bandwidth required for parallel computing. A 125 GOPS NoC-based parallel Processor with a bio-inspired visual attention engine (VAE) exploits both data and object-level parallelism while dissipating 583 mW by packet-based power management. The use of more PEs, VAE, and low latency NoC enables higher performance and power efficiency over the previous design. NoC-based parallel Processor consisting of 12 IPs: a Main Processor, 8 PE clusters (PECs), VAE, a matching accelerator (MA), and an external interface. The ARMlO-compatible 32b Main Processor controls the overall system operations. The VAE detects the feature points on the entire image by neural network algorithms like contour extraction. The 8 PECs perform data-intensive image processing applications such as filtering and histogram calculations. The MA accelerates nearest neighbor search to obtain a final recognition result in real-time. The DMA-like external interface distributes automatically the corresponding image data to each PEC to reduce system overhead. Each core is connected to the NoC via a network interface.
Marc Pollefeys - One of the best experts on this subject based on the ideXlab platform.
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a versatile stereo implementation on commodity graphics hardware
Real-time Imaging, 2005Co-Authors: Ruigang Yang, Marc PollefeysAbstract:This paper presents a detailed description of a real-time correlation-based stereo algorithm running completely on the graphics processing unit (GPU). This is important since it allows to free up the Main Processor for other tasks including high-level interpretation of the stereo results. We first introduce a two-view stereo algorithm that includes some advanced features such as adaptive windows and cross-checking. Then we extend it using a plane-sweep approach to allow multiple frames without rectification. By taking advantage of advanced features of recent GPUs the proposed algorithm runs in real-time. Our implementation running on an ATI Radeon 9800 graphics card achieves up to 289 million disparity evaluations per second including all the overhead to download images and read-back the disparity map, which is several times faster than commercially available CPU-based implementations.
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improved real time stereo on commodity graphics hardware
Computer Vision and Pattern Recognition, 2004Co-Authors: Ruigang Yang, Marc PollefeysAbstract:This paper presents a detailed description of an advanced real-time correlation-based stereo algorithm running completely on the graphics processing unit (GPU). This is important since it allows to free up the Main Processor for other tasks including high-level interpretation of the stereo results. Compared to previous GPU-based stereo implementations our implementation includes some advanced features such as adaptive windows and cross-checking. By taking advantage of advanced features of recent GPUs the proposed algorithm is also a lot faster than previous implementations. Our implementation running on an ATI Radeon 9800 graphics card achieves over 289 million disparity evaluations per second including all the overhead to download images and read-back the disparity map, which is several times faster than commercially available CPU-based implementations.
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multi resolution real time stereo on commodity graphics hardware
Computer Vision and Pattern Recognition, 2003Co-Authors: Ruigang Yang, Marc PollefeysAbstract:In this paper a stereo algorithm suitable for implementation on commodity graphics hardware is presented. This is important since it allows freeing up the Main Processor for other tasks including high-level interpretation of the stereo results. Our algorithm relies on the traditional sum-of-square-differences (SSD) dissimilarity measure between correlation windows. To achieve good results close to depth discontinuities as well as on low texture areas, a multi-resolution approach is used. The approach efficiently combines SSD measurements for windows of different sizes. Our implementation running on an NVIDIA GeForce4 graphics card achieves 50-70M disparity evaluations per second including all the overhead to download images and read-back the disparity map, which is equivalent to the fastest commercial CPU implementations available. An important advantage of our approach is that rectification is not necessary so that correspondences can just as easily be obtained for images that contain the epipoles. Another advantage is that this approach can easily be extended to multi-baseline stereo.
