The Experts below are selected from a list of 247731 Experts worldwide ranked by ideXlab platform
David V. Leaming - One of the best experts on this subject based on the ideXlab platform.
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Practice styles and preferences of ASCRS members--2003 survey
Journal of cataract and refractive surgery, 2004Co-Authors: David V. LeamingAbstract:A survey of the members of the American Society of Cataract and Refractive Surgery (ASCRS) with a United States ZIP code was performed in July 2003. Approximately 15.5% (985) of the 6350 questionnaires were returned for analysis. Three Main Profile questions were used in the cross-tabulation: age of the respondent, geographic location, and volume of cataract surgery per month. The refractive surgical questions were cross-tabulated for the volume of laser in situ keratomileusis. Results of the survey were compared with those in previous surveys of ASCRS members.
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Practice styles and preferences of ASCRS members—1997 survey
Journal of cataract and refractive surgery, 1998Co-Authors: David V. LeamingAbstract:A survey of the practice styles and preferences of members of the American Society of Cataract and Refractive Surgery with a United States ZIP code was performed in September 1997. Approximately 29% (1441) of the 5000 questionnaires mailed were returned by the November cut-off date. Three Main Profile questions were used to cross-tabulate data: age of the ophthalmologist, geographic location, and volume of cataract surgery per month. Current data were compared with data in previous annual surveys.
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Practice styles and preferences of ASCRS members--1996 survey.
Journal of cataract and refractive surgery, 1997Co-Authors: David V. LeamingAbstract:A survey of the practice styles and preferences of members of the American Society of Cataract and Refractive Surgery with a United States ZIP code was performed in September 1996. Approximately 26% (1440) of the 5520 questionnaires mailed were returned by the November cutoff date. Three Main Profile questions were used to cross-tabulate data: age of the ophthalmologist, geographic location, and volume of cataract surgery per month. Current data were compared with data in previous annual surveys.
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Practice styles and preferences of ASCRS members--1995 survey.
Journal of cataract and refractive surgery, 1996Co-Authors: David V. LeamingAbstract:A survey of the practice styles and preferences of the 1995 members of the American Society of Cataract and Refractive Surgery with a U.S. ZIP code was performed in September 1995. Approximately 27% (1500) of the 5500 questionnaires mailed were returned by the December cutoff date. Four Main Profile questions were used to cross-tabulate data: age of the ophthalmologist, geographic location, volume of cataract surgery per month, and volume of refractive surgery per month. Current data were compared with data in previous annual surveys.
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Practice styles and preferences of ASCRS members. 1994 survey
Journal of cataract and refractive surgery, 1995Co-Authors: David V. LeamingAbstract:A survey of the practice styles and preferences of the 1994 members of the American Society of Cataract and Refractive Surgery who had a U.S. ZIP code was performed in September 1994. Approximately 32% (1569) of the 4849 questionnaires mailed out were returned by the November cutoff date. Four Main Profile questions were used to cross-tabulate: age of the ophthalmologist, geographic location, volume of cataract surgery per month, and volume of refractive surgery per month. This report also compared the data with previously published surveys.
Kaiyuan Jan - One of the best experts on this subject based on the ideXlab platform.
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a highly integrated 8mw h 264 avc Main Profile real time cif video decoder on a 16mhz soc platform
Asia and South Pacific Design Automation Conference, 2007Co-Authors: Huankai Peng, Jian-wen Chen, Chunhsin Lee, Yunghung Chang, Shengtsung Hsu, Yuanchun Lin, Ping Chao, Weicheng Hung, Kaiyuan JanAbstract:We present a hardwired decoder prototype for H.264/AVC Main Profile video. Our design takes as its input compressed H.264/AVC bit-stream and produces as its output video frames ready for display. We wrap the decoder core with an AMBA-AHB bus interface and integrate it into a multimedia SoC platform. Several architectural innovations at both IP and system levels are proposed to achieve very high performance at very low operating frequency. Running at 16MHz, our FPGA demo system is able to real-time decode CIF (352 times 288) video at 30 frames per second. Moreover, we take system cost into consideration such that only a single external SDRAM is needed and memory traffic minimized.
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ASP-DAC - A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform
2007 Asia and South Pacific Design Automation Conference, 2007Co-Authors: Huankai Peng, Jian-wen Chen, Chunhsin Lee, Yunghung Chang, Shengtsung Hsu, Yuanchun Lin, Ping Chao, Weicheng Hung, Kaiyuan JanAbstract:We present a hardwired decoder prototype for H.264/AVC Main Profile video. Our design takes as its input compressed H.264/AVC bit-stream and produces as its output video frames ready for display. We wrap the decoder core with an AMBA-AHB bus interface and integrate it into a multimedia SoC platform. Several architectural innovations at both IP and system levels are proposed to achieve very high performance at very low operating frequency. Running at 16MHz, our FPGA demo system is able to real-time decode CIF (352 times 288) video at 30 frames per second. Moreover, we take system cost into consideration such that only a single external SDRAM is needed and memory traffic minimized.
Jian-wen Chen - One of the best experts on this subject based on the ideXlab platform.
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a high throughput fully hardwired cabac encoder for qfhd h 264 avc Main Profile video
IEEE Transactions on Consumer Electronics, 2010Co-Authors: Jian-wen Chen, Po-sheng Liu, Youn-long LinAbstract:We propose a very high-throughput fully hardwired CABAC encoder for ultra-high resolution video. Our architecture includes hardwired circuits for binarization, context modeling, neighbor data access, and a six-stage pipelined binary arithmetic encoder (BAE). Our BAE can encode multiple bins per cycle. In order to keep up with the BAE throughput, we propose acceleration methods for the bin and context index generations of several types of frequent syntax elements (SE). We further propose a novel architecture that shortens the critical path of renormalization and bitstream generation. Our design can encode 1.42 bins per cycle on the average, and it achieves a throughput of 315 Mbin/sec. Simulation results show that it can real-time encode QFHD (3840×2176) video at 30 fps or 1080 HD (1920×1088) at 60 fps for H.264/AVC Main Profile, level 5.1 by running at 222 MHz. We have successfully integrated the proposed CABAC encoder into an H.264/AVC encoder system using an SoC platform.
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A high-throughput fully hardwired CABAC encoder for QFHD H.264/AVC Main Profile video
IEEE Transactions on Consumer Electronics, 2010Co-Authors: Jian-wen Chen, Po-sheng Liu, Youn-long LinAbstract:We propose a very high-throughput fully hardwired CABAC encoder for ultra-high resolution video. Our architecture includes hardwired circuits for binarization, context modeling, neighbor data access, and a six-stage pipelined binary arithmetic encoder (BAE). Our BAE can encode multiple bins per cycle. In order to keep up with the BAE throughput, we propose acceleration methods for the bin and context index generations of several types of frequent syntax elements (SE). We further propose a novel architecture that shortens the critical path of renormalization and bitstream generation. Our design can encode 1.42 bins per cycle on the average, and it achieves a throughput of 315 Mbin/sec. Simulation results show that it can real-time encode QFHD (3840×2176) video at 30 fps or 1080 HD (1920×1088) at 60 fps for H.264/AVC Main Profile, level 5.1 by running at 222 MHz. We have successfully integrated the proposed CABAC encoder into an H.264/AVC encoder system using an SoC platform.
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a highly integrated 8mw h 264 avc Main Profile real time cif video decoder on a 16mhz soc platform
Asia and South Pacific Design Automation Conference, 2007Co-Authors: Huankai Peng, Jian-wen Chen, Chunhsin Lee, Yunghung Chang, Shengtsung Hsu, Yuanchun Lin, Ping Chao, Weicheng Hung, Kaiyuan JanAbstract:We present a hardwired decoder prototype for H.264/AVC Main Profile video. Our design takes as its input compressed H.264/AVC bit-stream and produces as its output video frames ready for display. We wrap the decoder core with an AMBA-AHB bus interface and integrate it into a multimedia SoC platform. Several architectural innovations at both IP and system levels are proposed to achieve very high performance at very low operating frequency. Running at 16MHz, our FPGA demo system is able to real-time decode CIF (352 times 288) video at 30 frames per second. Moreover, we take system cost into consideration such that only a single external SDRAM is needed and memory traffic minimized.
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ASP-DAC - A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform
2007 Asia and South Pacific Design Automation Conference, 2007Co-Authors: Huankai Peng, Jian-wen Chen, Chunhsin Lee, Yunghung Chang, Shengtsung Hsu, Yuanchun Lin, Ping Chao, Weicheng Hung, Kaiyuan JanAbstract:We present a hardwired decoder prototype for H.264/AVC Main Profile video. Our design takes as its input compressed H.264/AVC bit-stream and produces as its output video frames ready for display. We wrap the decoder core with an AMBA-AHB bus interface and integrate it into a multimedia SoC platform. Several architectural innovations at both IP and system levels are proposed to achieve very high performance at very low operating frequency. Running at 16MHz, our FPGA demo system is able to real-time decode CIF (352 times 288) video at 30 frames per second. Moreover, we take system cost into consideration such that only a single external SDRAM is needed and memory traffic minimized.
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ISCAS (5) - A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC
2005 IEEE International Symposium on Circuits and Systems, 1Co-Authors: Jian-wen Chen, Cheng-ru Chang, Youn-long LinAbstract:We propose a hardware accelerator for context-based adaptive binary arithmetic decoding (CABAC) in H.264/AVC. We also propose an efficient memory system for easy integration with other components such as motion compensation and IDCT. We develop an efficient finite state machine so that our design can generate one bit every 2 to 3 clock cycles. Experimental result with FPGA prototyping shows that our design is sufficient to decode Main Profile CIF video streams at 30 fps.
Sergio Bampi - One of the best experts on this subject based on the ideXlab platform.
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Motion vector predictor architecture for H.264/AVC Main Profile targeting HDTV 1080p
2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2010Co-Authors: Franco Valdez, Luciano Agostini, Bruno Zatt, Arnaldo Azevedo, Sergio BampiAbstract:This article presents an architecture for a motion vectors predictor using H.264/AVC standard Main Profile. The motion vectors predictor is one of the most important modules of motion compensation. This architecture was developed to work at 100 MHz, providing a processing rate capable of decoding HDTV in real time. The hardware is composed by a bank of registers and a state machine operating over the registered data. The design was synthesized for FPGA Xilinx Virtex II-PRO and ASIC TSMC 0,18 μm technology reaching maximum frequency of operation of 133 MHz and 129 MHz, respectively.
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Design and FPGA prototyping of a H: 264/AVC Main Profile decoder for HDTV
Journal of the Brazilian Computer Society, 2007Co-Authors: Luciano Agostini, Arnaldo Pereira De Azevedo Filho, Wagston Tassoni Staehler, Ana Cristina Medina Pinto, Roger Porto, Sergio Bampi, Vagner Santos Da Rosa, Bruno Zatt, Altamiro Amadeu SusinAbstract:This paper presents the architecture, design, validation, and hardware prototyping of the Main architectural blocks of Main Profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a Main Profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.
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motion compensation decoder architecture for h 264 avc Main Profile targeting hdtv
2006 IFIP International Conference on Very Large Scale Integration, 2006Co-Authors: Arnaldo Azevedo, Luciano Agostini, Bruno Zatt, Sergio BampiAbstract:This work presents the design, the validation and the prototyping of a motion compensation architecture for a H.264/AVC video decoder. The designed architecture supports the Main Profile level 4.0 and it targets high resolution applications, like HDTV. This design considers the sample processing of the motion compensation block, which includes quarter-pel interpolation, weighted prediction, average to bi-predictive processing and clipping. The architecture processes luma and chroma samples in parallel, with independent luma and chroma datapaths. The design uses a single interpolator to process bi-predictive macroblocks. The design was synthesized to FPGA and standard cell technologies. The synthesis results had indicated that this architecture reaches 100 MHz in both technologies, allowing real time to decode HDTV videos with 1920times1080 pixels. The prototype was targeted to a Xilinx Virtex-II PRO FPGA
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fpga design of a h 264 avc Main Profile decoder for hdtv
Field-Programmable Logic and Applications, 2006Co-Authors: Luciano Agostini, Sergio Bampi, Vagner Santos Da Rosa, A Azevedo P Filho, E A Berriel, T G S Santos, Altamiro Amadeu SusinAbstract:This paper presents the architecture, design, validation, and prototyping of inverse transforms and quantization, intra prediction, motion compensation and loop filter, for a Main Profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations down to prototyping. The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million of samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.
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FPL - FPGA Design of A H.264/AVC Main Profile Decoder for HDTV
2006 International Conference on Field Programmable Logic and Applications, 2006Co-Authors: Luciano Agostini, Arnaldo Pereira De Azevedo Filho, Sergio Bampi, Vagner Santos Da Rosa, E A Berriel, T G S Santos, Altamiro Amadeu SusinAbstract:This paper presents the architecture, design, validation, and prototyping of inverse transforms and quantization, intra prediction, motion compensation and loop filter, for a Main Profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations down to prototyping. The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million of samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.
Luciano Agostini - One of the best experts on this subject based on the ideXlab platform.
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Motion vector predictor architecture for H.264/AVC Main Profile targeting HDTV 1080p
2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2010Co-Authors: Franco Valdez, Luciano Agostini, Bruno Zatt, Arnaldo Azevedo, Sergio BampiAbstract:This article presents an architecture for a motion vectors predictor using H.264/AVC standard Main Profile. The motion vectors predictor is one of the most important modules of motion compensation. This architecture was developed to work at 100 MHz, providing a processing rate capable of decoding HDTV in real time. The hardware is composed by a bank of registers and a state machine operating over the registered data. The design was synthesized for FPGA Xilinx Virtex II-PRO and ASIC TSMC 0,18 μm technology reaching maximum frequency of operation of 133 MHz and 129 MHz, respectively.
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Design and FPGA prototyping of a H: 264/AVC Main Profile decoder for HDTV
Journal of the Brazilian Computer Society, 2007Co-Authors: Luciano Agostini, Arnaldo Pereira De Azevedo Filho, Wagston Tassoni Staehler, Ana Cristina Medina Pinto, Roger Porto, Sergio Bampi, Vagner Santos Da Rosa, Bruno Zatt, Altamiro Amadeu SusinAbstract:This paper presents the architecture, design, validation, and hardware prototyping of the Main architectural blocks of Main Profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a Main Profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.
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design and fpga prototyping of a h 264 avc Main Profile decoder for hdtv
Journal of the Brazilian Computer Society, 2007Co-Authors: Luciano Agostini, Arnaldo Pereira De Azevedo Filho, Ana Cristina Medina Pinto, Wagston Tassoni Staehle, Roge Porto, Vagner Santos Da Rosa, Sergio Ampi, Altamiro Amadeu SusiAbstract:This paper presents the architecture, design, validation, and hardware prototyping of the Main architectural blocks of Main Profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a Main Profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.
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motion compensation decoder architecture for h 264 avc Main Profile targeting hdtv
2006 IFIP International Conference on Very Large Scale Integration, 2006Co-Authors: Arnaldo Azevedo, Luciano Agostini, Bruno Zatt, Sergio BampiAbstract:This work presents the design, the validation and the prototyping of a motion compensation architecture for a H.264/AVC video decoder. The designed architecture supports the Main Profile level 4.0 and it targets high resolution applications, like HDTV. This design considers the sample processing of the motion compensation block, which includes quarter-pel interpolation, weighted prediction, average to bi-predictive processing and clipping. The architecture processes luma and chroma samples in parallel, with independent luma and chroma datapaths. The design uses a single interpolator to process bi-predictive macroblocks. The design was synthesized to FPGA and standard cell technologies. The synthesis results had indicated that this architecture reaches 100 MHz in both technologies, allowing real time to decode HDTV videos with 1920times1080 pixels. The prototype was targeted to a Xilinx Virtex-II PRO FPGA
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fpga design of a h 264 avc Main Profile decoder for hdtv
Field-Programmable Logic and Applications, 2006Co-Authors: Luciano Agostini, Sergio Bampi, Vagner Santos Da Rosa, A Azevedo P Filho, E A Berriel, T G S Santos, Altamiro Amadeu SusinAbstract:This paper presents the architecture, design, validation, and prototyping of inverse transforms and quantization, intra prediction, motion compensation and loop filter, for a Main Profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations down to prototyping. The architectures were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million of samples per second and, in the worst case, they are able to process 64 HDTV frames (1080×1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.
