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Mau-chung Frank Chang - One of the best experts on this subject based on the ideXlab platform.
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a 16 gb s 14 7 mw tri band cognitive serial link transmitter with forwarded clock to enable pam 16 256 qam and channel response detection
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Yuan Du, Chien-heng Wong, Jieqiong Du, Boyu Hu, Po-tsang Huang, Li Du, Yilei Li, Mau-chung Frank ChangAbstract:A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, Data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the Maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a Maximum Data Rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 $\mu \text{W}$ /Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second Data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.
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a 16gb s 14 7mw tri band cognitive serial link transmitter with forwarded clock to enable pam 16 256 qam and channel response detection in 28 nm cmos
Symposium on VLSI Circuits, 2016Co-Authors: Weihan Cho, Chien-heng Wong, Po-tsang Huang, Yanghyo Kim, Zuowzun Chen, Sheau Jiung Lee, Mau-chung Frank ChangAbstract:A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, Data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the Maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a Maximum Data Rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 µW/Gb/s/dB considering channel condition.
Chien-heng Wong - One of the best experts on this subject based on the ideXlab platform.
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a 16 gb s 14 7 mw tri band cognitive serial link transmitter with forwarded clock to enable pam 16 256 qam and channel response detection
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Yuan Du, Chien-heng Wong, Jieqiong Du, Boyu Hu, Po-tsang Huang, Li Du, Yilei Li, Mau-chung Frank ChangAbstract:A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, Data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the Maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a Maximum Data Rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 $\mu \text{W}$ /Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second Data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.
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a 16gb s 14 7mw tri band cognitive serial link transmitter with forwarded clock to enable pam 16 256 qam and channel response detection in 28 nm cmos
Symposium on VLSI Circuits, 2016Co-Authors: Weihan Cho, Chien-heng Wong, Po-tsang Huang, Yanghyo Kim, Zuowzun Chen, Sheau Jiung Lee, Mau-chung Frank ChangAbstract:A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, Data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the Maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a Maximum Data Rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 µW/Gb/s/dB considering channel condition.
Po-tsang Huang - One of the best experts on this subject based on the ideXlab platform.
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a 16 gb s 14 7 mw tri band cognitive serial link transmitter with forwarded clock to enable pam 16 256 qam and channel response detection
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Yuan Du, Chien-heng Wong, Jieqiong Du, Boyu Hu, Po-tsang Huang, Li Du, Yilei Li, Mau-chung Frank ChangAbstract:A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, Data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the Maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a Maximum Data Rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 $\mu \text{W}$ /Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second Data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.
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a 16gb s 14 7mw tri band cognitive serial link transmitter with forwarded clock to enable pam 16 256 qam and channel response detection in 28 nm cmos
Symposium on VLSI Circuits, 2016Co-Authors: Weihan Cho, Chien-heng Wong, Po-tsang Huang, Yanghyo Kim, Zuowzun Chen, Sheau Jiung Lee, Mau-chung Frank ChangAbstract:A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, Data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the Maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a Maximum Data Rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 µW/Gb/s/dB considering channel condition.
Tadahiro Kuroda - One of the best experts on this subject based on the ideXlab platform.
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a 50 mbps pin 12 input output 40 nsec latency wireless connector using a transmission line coupler with compact serdes ic in 180 nm cmos
International Conference on Electronics Circuits and Systems, 2020Co-Authors: Kohei Ando, Kazuhisa Akatsuka, Chaoran Cheng, Tomoya Arakawa, Kota Shiba, Mototsugu Hamada, Tadahiro KurodaAbstract:We present a prototype chip that enables 12-input/12-output wireless connector with only one transmission line coupler (TLC). The chip is capable of both the transmit mode and the receive mode operations, which can be set by an external pin. In the transmit mode, it serializes 12 input signals and drives the primary side of a TLC with an integRated 2 GHz clock signal. In the receive mode, it receives the output of the secondary side of the TLC, deserializes it and outputs 12 signals. The chip is designed and fabricated in a 180 nm CMOS process. The single supply voltage of 1.8 V is used by the chip, which draws 60 mA and 73 mA in the transmit mode and receive mode, respectively. The Maximum Data Rate per pin is 50 Mbps, namely the total Maximum Data Rate is 600 Mbps. Manchester code is employed so that simple clock and Data recovery (CDR) circuits implemented by combinational logic circuits geneRate a clock signal in the receive mode. No phase locked loop-type CDR is required. Compared with the conventional one, the chip achieves 78% miniaturization, 67% power reduction and 97% latency reduction. Measurement results show that a wireless connector system using the chips is operational even when the supply voltages of the primary side and the secondary side have a mismatch of +/-11%. The wireless connector is applied to an audio system with 2 streams transferred by a single multi-bit connector. The fidelity of the sound is as good as when they are connected by 2 wires.
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a 0 15mm thick non contact connector for mipi using vertical directional coupler
International Solid-State Circuits Conference, 2013Co-Authors: Wataru Mizuhara, Noriyuki Miura, Hiroki Ishikuro, Tsunaaki Shidei, Atsutake Kosuge, Tsutomu Takeya, Masao Taguchi, Tadahiro KurodaAbstract:As silicon chip performance continues to increase, the interconnection capabilities should also be improved to achieve higher overall system performance. This paper proposes a new, small-size and high-speed non-contact interconnect between printed circuit boards (PCBs) using a vertical directional coupler (VDC), which has actually been applied to a liquid crystal display (LCD) driver board. The feasibility of a millimeter-range non-contact interface using a directional coupler was studied previously [1]. In this paper, two signal ports have been implemented in one coupler by best utilizing the characteristics of VDC. The coupler size is 5mm × 2.25mm, and the gap between the couplers is about 75μm, which corresponds to the twofold thickness of a soldering resist on PCB and the adhesive material in between. The transmitter transforms the Data sequence from Non-Return-to-Zero (NRZ) into pulses in order to reduce the level of DC components. This achieves a power saving of 1.47pJ/b, and the pulses are sent to the coupler in differential mode to prevent electromagnetic interference (EMI). The measured speed was 4.6Gb/s per coupler to achieve the MIPI's Maximum speed of 6Gb/s with two couplers. Conventional connectors have housings to protect contact elements or to provide mechanical support for plug-in and out. However, these housings make it difficult to achieve the smallest possible systems because they require extra space. In addition, they sometimes make the PCB trace longer, which deterioRates the Maximum Data Rate. The method we have developed involves delineating VDC on PCB or a flexible printed circuit (FPC) to connect boards without housings and with the minimum distance. As a result, this interconnect scheme is advantageous not only because it saves space but also because it makes it easier to build systems, even those that contain a large number of built-in connectors. Thus, the proposed non-contact interconnect is suitable for future small-size systems.
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a 2 5gb s ch 4pam inductive coupling transceiver for non contact memory card
International Solid-State Circuits Conference, 2010Co-Authors: Shusuke Kawai, Hiroki Ishikuro, Tadahiro KurodaAbstract:An inductive-coupling link has been studied for inter-chip communications in System-in-a-Package [1]. Its communication distance extends millimeter ranges [2,3] and it can be used as a wireless interface for non-contact memory cards. High speed and low power communication can be performed in the inductive-coupling link because of the removal of highly capacitive ESD protection devices [1]. The wireless interface eliminates mechanical contacts resulting in high reliability. Target Data Rate is 2.5Gb/s/ch which is 12.5x higher than that of a commercial memory card and target communication range is 0.5mm to 1mm, considering the allowance of card insertion. The Maximum Data Rate of the inductive-coupling link demonstRated in [3] at 1mm distance was 160Mb/s/ch. A theoretical limit is 1Gb/s/ch since self resonant frequency of an on-chip inductor of 3GHz. To increase the self resonant frequency, the inductor is moved off chip to a flexible circuit board to reduce parasitic capacitance. The self resonant frequency of 1mm diameter inductor is increased to 4GHz corresponding to a signal Data Rate of 1.25Gb/s/ch. Additionally, the number of bit per symbol is increased to 2 by 4 pulse amplitude modulation (4PAM) and a Data Rate of 2.5Gb/s/ch is achieved. But to communicate by using 4PAM in the inductive-coupling link, issues listed below must be solved. First, the communication range is limited to 0.95mm to 1mm. The amplitude of the received signal is inversely proportional to the communication distance, and therefore, received signal cannot be converted to a correct Data without adjusting the input threshold voltages of a receiver. Second, the pulse width is narrower in 4PAM and thus synchronization on the receiver side is difficult.
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an attachable wireless chip access interface for arbitrary Data Rate using pulse based lnductive coupling through lsi package
International Solid-State Circuits Conference, 2007Co-Authors: Hiroki Ishikuro, T Sugahara, Tadahiro KurodaAbstract:A wireless logic-probing system is presented as one of the applications of the millimeter-range carrierless inductive-coupling technique. A pulse transceiver for a wireless probe and its target LSI is fabricated using a 0.25mum standard CMOS logic process. A Maximum Data Rate of 20Mb/s and a communication range of 1.2mm is achieved.
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analysis and design of inductive coupling and transceiver circuit for inductive inter chip wireless superconnect
Symposium on VLSI Circuits, 2005Co-Authors: Noriyuki Miura, Takayasu Sakurai, Daisuke Mizoguchi, Tadahiro KurodaAbstract:A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, Data Rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when Data remains the same. A test chip was fabricated in 0.35-μm CMOS technology. Accuracy of the models is verified. Bit-error Rate is investigated for various inductor layouts and communication distance. The Maximum Data Rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 μm in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm 2 .
Weihan Cho - One of the best experts on this subject based on the ideXlab platform.
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a 16gb s 14 7mw tri band cognitive serial link transmitter with forwarded clock to enable pam 16 256 qam and channel response detection in 28 nm cmos
Symposium on VLSI Circuits, 2016Co-Authors: Weihan Cho, Chien-heng Wong, Po-tsang Huang, Yanghyo Kim, Zuowzun Chen, Sheau Jiung Lee, Mau-chung Frank ChangAbstract:A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, Data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the Maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a Maximum Data Rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 µW/Gb/s/dB considering channel condition.