The Experts below are selected from a list of 206772 Experts worldwide ranked by ideXlab platform
Yuan Xie - One of the best experts on this subject based on the ideXlab platform.
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kiln closing the performance gap between systems with and without persistence support
International Symposium on Microarchitecture, 2013Co-Authors: Jishen Zhao, Yuan Xie, Doe Hyun Yoon, Norman P JouppiAbstract:Persistent Memory is an emerging technology which allows in-Memory persistent data objects to be updated at much higher throughput than when using disks as persistent storage. Previous persistent Memory Designs use logging or copy-on-write mechanisms to update persistent data, which unfortunately reduces the system performance to roughly half that of a native system with no persistence support. One of the great challenges in this application class is therefore how to efficiently enable atomic, consistent, and durable updates to ensure data persistence that survives application and/or system failures. Our goal is to Design a persistent Memory system with performance very close to that of a native system. We propose Kiln, a persistent Memory Design that adopts a nonvolatile cache and a nonvolatile main Memory to enable atomic in-place updates without logging or copy-on-write. Our evaluation shows that Kiln can achieve 2× performance improvement compared with NVRAM-based persistent Memory with write-ahead logging. In addition, our Design has numerous practical advantages: a simple and intuitive abstract interface, microarchitecture-level optimizations, fast recovery from failures, and eliminating redundant writes to nonvolatile storage media.
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low power multi level cell resistive Memory Design with incomplete data mapping
International Conference on Computer Design, 2013Co-Authors: Dimin Niu, Qiaosha Zou, Yuan XieAbstract:Phase change Memory (PCM) has been widely studied as a potential DRAM alternative. The multi-level cell (MLC) can further increase the Memory density and reduce the fabrication cost by storing multiple bits in a single cell. Nevertheless, large write power, high write latency, as well as reliability issue resulted from the resistance drift, bring in challenges for MLC PCM based Memory Design. In contrast, the emerging Resistive Random Access Memory (ReRAM), which has similar MLC property as PCM, demonstrates better performance and energy efficiency compared to PCM. In addition, due to the physical switching behaviors of ReRAM cell, the resistance drift phenomenon does not exist. In this paper, we propose a low power MLC ReRAM Design. We first study the programming method of MLC ReRAM and identify that programming latency and energy are highly dependent on the data pattern written to the cell. Based on this observation, we propose incomplete data mapping (IDM), which maps an eight-level-cell into six states to prevent the time/energy consuming data patterns from appearing in the cell. Furthermore, in order to improve endurance of MLC RAM, which is much smaller than single-level cell (SLC) ReRM due to the complex programming method, we propose Dynamic Data ReMapping (DDRM) to selectively regulate Memory blocks from IDM state back to complete data mapping (CDM) state. We demonstrate that the proposed Design can work effectively with existing error-correction schemes but requires much smaller space overhead. Experimental results show that, IDM can reduce the energy performance by at most 15% with negligible performance overhead. By combining the DDRM with existing error-correction scheme, DDRM can improve the Memory lifetime by 2.75× compared with conventional Memory architectures.
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understanding the trade offs in multi level cell reram Memory Design
Design Automation Conference, 2013Co-Authors: Dimin Niu, Norman P Jouppi, Naveen Muralimanohar, Yuan XieAbstract:Resistive Random Access Memory (ReRAM) is one of the most promising emerging Memory technologies as a potential replacement for DRAM Memory and/or NAND Flash. Multi-level cell (MLC) ReRAM, which can store multiple bits in a single ReRAM cell, can further improve density and reduce cost-per-bit, and therefore has recently been investigated extensively. However, the majority of the prior studies on MLC ReRAM are at the device level. The Design implications for MLC ReRAM at the circuit and system levels remain to be explored. This paper aim to provide the first comprehensive investigation of the Design trade-offs involved in MLC ReRAM. Our study indicates that different resistance allocation schemes, programming strategies, peripheral Designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM Design against MLC phase-change Memory (PCM) and multi-layer cross-point ReRAM Design, and point out why multi-level ReRAM is appealing; second we further explore the Design space for MLC ReRAM.
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adams adaptive mlc slc phase change Memory Design for file storage
Asia and South Pacific Design Automation Conference, 2011Co-Authors: Xiangyu Dong, Yuan XieAbstract:Phase-change Memory (PCM) is an emerging Memory technology that has made rapid progress in the recent years, and surpasses other technologies such as FeRAM and MRAM in terms of scalability. Recently, the feasibility of multi-level cell (MLC) for PCM, which enables a cell to store more than one bit of digital data, has also been shown. This new property makes PCM more competitive and considered as the successor of the NAND flash technology, which also has the MLC capability but does not have an easy scaling path to reach higher densities. However, the MLC capability of PCM comes with the penalty of longer programming time and shortened cell lifetime compared to its single-level cell (SLC) mode. Therefore, it suggests an adaptive MLC/SLC reconfigurable PCM Design that can exploit the fast SLC access speed and the large MLC capacity with the awareness of workload characteristics and lifetime requirements. In this work, a circuit-level adaptive MLC/SLC PCM array is Designed at first, the management policy of MLC/SLC mode is proposed, and finally the performance and lifetime of a novel PCM-based SSD with run-time MLC/SLC reconfiguration ability is evaluated1.
Zhenyu Sun - One of the best experts on this subject based on the ideXlab platform.
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cross layer racetrack Memory Design for ultra high density and low power consumption
Design Automation Conference, 2013Co-Authors: Zhenyu SunAbstract:The racetrack Memory technology utilizes magnetic domains along a nanoscopic wire to obtain ultra-high data storage density. The recent success in the planar racetrack nanowire promised its fabrication feasibility and future scalability, bringing more Design challenges and opportunities. In this paper, we initialize the optimization of racetrack Memory embracing Design considerations across multiple layers, including cell Design, array structure, architecture organization, and data management. Our evaluation shows that racetrack Memory based cache can achieve 6.4x area reduction, 25% performance enhancement, and 62% energy saving, compared to STT-RAM cache Design. The benefit over SRAM technology is even more significant.
Dimin Niu - One of the best experts on this subject based on the ideXlab platform.
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low power multi level cell resistive Memory Design with incomplete data mapping
International Conference on Computer Design, 2013Co-Authors: Dimin Niu, Qiaosha Zou, Yuan XieAbstract:Phase change Memory (PCM) has been widely studied as a potential DRAM alternative. The multi-level cell (MLC) can further increase the Memory density and reduce the fabrication cost by storing multiple bits in a single cell. Nevertheless, large write power, high write latency, as well as reliability issue resulted from the resistance drift, bring in challenges for MLC PCM based Memory Design. In contrast, the emerging Resistive Random Access Memory (ReRAM), which has similar MLC property as PCM, demonstrates better performance and energy efficiency compared to PCM. In addition, due to the physical switching behaviors of ReRAM cell, the resistance drift phenomenon does not exist. In this paper, we propose a low power MLC ReRAM Design. We first study the programming method of MLC ReRAM and identify that programming latency and energy are highly dependent on the data pattern written to the cell. Based on this observation, we propose incomplete data mapping (IDM), which maps an eight-level-cell into six states to prevent the time/energy consuming data patterns from appearing in the cell. Furthermore, in order to improve endurance of MLC RAM, which is much smaller than single-level cell (SLC) ReRM due to the complex programming method, we propose Dynamic Data ReMapping (DDRM) to selectively regulate Memory blocks from IDM state back to complete data mapping (CDM) state. We demonstrate that the proposed Design can work effectively with existing error-correction schemes but requires much smaller space overhead. Experimental results show that, IDM can reduce the energy performance by at most 15% with negligible performance overhead. By combining the DDRM with existing error-correction scheme, DDRM can improve the Memory lifetime by 2.75× compared with conventional Memory architectures.
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understanding the trade offs in multi level cell reram Memory Design
Design Automation Conference, 2013Co-Authors: Dimin Niu, Norman P Jouppi, Naveen Muralimanohar, Yuan XieAbstract:Resistive Random Access Memory (ReRAM) is one of the most promising emerging Memory technologies as a potential replacement for DRAM Memory and/or NAND Flash. Multi-level cell (MLC) ReRAM, which can store multiple bits in a single ReRAM cell, can further improve density and reduce cost-per-bit, and therefore has recently been investigated extensively. However, the majority of the prior studies on MLC ReRAM are at the device level. The Design implications for MLC ReRAM at the circuit and system levels remain to be explored. This paper aim to provide the first comprehensive investigation of the Design trade-offs involved in MLC ReRAM. Our study indicates that different resistance allocation schemes, programming strategies, peripheral Designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM Design against MLC phase-change Memory (PCM) and multi-layer cross-point ReRAM Design, and point out why multi-level ReRAM is appealing; second we further explore the Design space for MLC ReRAM.
Ankit Singh Rawat - One of the best experts on this subject based on the ideXlab platform.
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associative Memory using dictionary learning and expander decoding
arXiv: Machine Learning, 2016Co-Authors: Arya Mazumdar, Ankit Singh RawatAbstract:An associative Memory is a framework of content-addressable Memory that stores a collection of message vectors (or a dataset) over a neural network while enabling a neurally feasible mechanism to recover any message in the dataset from its noisy version. Designing an associative Memory requires addressing two main tasks: 1) learning phase: given a dataset, learn a concise representation of the dataset in the form of a graphical model (or a neural network), 2) recall phase: given a noisy version of a message vector from the dataset, output the correct message vector via a neurally feasible algorithm over the network learnt during the learning phase. This paper studies the problem of Designing a class of neural associative memories which learns a network representation for a large dataset that ensures correction against a large number of adversarial errors during the recall phase. Specifically, the associative memories Designed in this paper can store dataset containing $\exp(n)$ $n$-length message vectors over a network with $O(n)$ nodes and can tolerate $\Omega(\frac{n}{{\rm polylog} n})$ adversarial errors. This paper carries out this Memory Design by mapping the learning phase and recall phase to the tasks of dictionary learning with a square dictionary and iterative error correction in an expander code, respectively.
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associative Memory using dictionary learning and expander decoding
National Conference on Artificial Intelligence, 2016Co-Authors: Arya Mazumdar, Ankit Singh RawatAbstract:An associative Memory is a framework of content-addressable Memory that stores a collection of message vectors (or a dataset) over a neural network while enabling a neurally feasible mechanism to recover any message in the dataset from its noisy version. Designing an associative Memory requires addressing two main tasks: 1) learning phase: given a dataset, learn a concise representation of the dataset in the form of a graphical model (or a neural network), 2) recall phase: given a noisy version of a message vector from the dataset, output the correct message vector via a neurally feasible algorithm over the network learnt during the learning phase. This paper studies the problem of Designing a class of neural associative memories which learns a network representation for a large dataset that ensures correction against a large number of adversarial errors during the recall phase. Specifically, the associative memories Designed in this paper can store dataset containing exp( n ) n -length message vectors over a network with O ( n ) nodes and can tolerate Ω( n / polylog) adversarial errors. This paper carries out this Memory Design by mapping the learning phase and recall phase to the tasks of dictionary learning with a square dictionary and iterative error correction in an expander code, respectively.
Norman P Jouppi - One of the best experts on this subject based on the ideXlab platform.
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kiln closing the performance gap between systems with and without persistence support
International Symposium on Microarchitecture, 2013Co-Authors: Jishen Zhao, Yuan Xie, Doe Hyun Yoon, Norman P JouppiAbstract:Persistent Memory is an emerging technology which allows in-Memory persistent data objects to be updated at much higher throughput than when using disks as persistent storage. Previous persistent Memory Designs use logging or copy-on-write mechanisms to update persistent data, which unfortunately reduces the system performance to roughly half that of a native system with no persistence support. One of the great challenges in this application class is therefore how to efficiently enable atomic, consistent, and durable updates to ensure data persistence that survives application and/or system failures. Our goal is to Design a persistent Memory system with performance very close to that of a native system. We propose Kiln, a persistent Memory Design that adopts a nonvolatile cache and a nonvolatile main Memory to enable atomic in-place updates without logging or copy-on-write. Our evaluation shows that Kiln can achieve 2× performance improvement compared with NVRAM-based persistent Memory with write-ahead logging. In addition, our Design has numerous practical advantages: a simple and intuitive abstract interface, microarchitecture-level optimizations, fast recovery from failures, and eliminating redundant writes to nonvolatile storage media.
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understanding the trade offs in multi level cell reram Memory Design
Design Automation Conference, 2013Co-Authors: Dimin Niu, Norman P Jouppi, Naveen Muralimanohar, Yuan XieAbstract:Resistive Random Access Memory (ReRAM) is one of the most promising emerging Memory technologies as a potential replacement for DRAM Memory and/or NAND Flash. Multi-level cell (MLC) ReRAM, which can store multiple bits in a single ReRAM cell, can further improve density and reduce cost-per-bit, and therefore has recently been investigated extensively. However, the majority of the prior studies on MLC ReRAM are at the device level. The Design implications for MLC ReRAM at the circuit and system levels remain to be explored. This paper aim to provide the first comprehensive investigation of the Design trade-offs involved in MLC ReRAM. Our study indicates that different resistance allocation schemes, programming strategies, peripheral Designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM Design against MLC phase-change Memory (PCM) and multi-layer cross-point ReRAM Design, and point out why multi-level ReRAM is appealing; second we further explore the Design space for MLC ReRAM.