The Experts below are selected from a list of 276 Experts worldwide ranked by ideXlab platform

Mani Srivastava - One of the best experts on this subject based on the ideXlab platform.

  • a system for coarse grained Memory protection in tiny embedded processors
    Design Automation Conference, 2007
    Co-Authors: Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
    Abstract:

    Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of Memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides Memory protection in tiny embedded processors. . Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict Memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory Map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory Map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected Memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of Memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.

  • DAC - A system for coarse grained Memory protection in tiny embedded processors
    Proceedings of the 44th annual conference on Design automation - DAC '07, 2007
    Co-Authors: Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
    Abstract:

    Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of Memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides Memory protection in tiny embedded processors. . Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict Memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory Map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory Map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected Memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of Memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.

  • harbor software based Memory protection for sensor nodes
    Information Processing in Sensor Networks, 2007
    Co-Authors: Ram Kumar, Eddie Kohler, Mani Srivastava
    Abstract:

    Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware Memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a Memory protection system that prevents many forms of Memory corruption. We use software based fault isolation ("sandboxing") to restrict application Memory accesses and control flow to protection domains within the address space. A flexible and efficient Memory Map data structure records ownership and layout information for Memory regions; writes are validated using the Memory Map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected Memory region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand- boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented Memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.

  • IPSN - Harbor: software-based Memory protection for sensor nodes
    Proceedings of the 6th international conference on Information processing in sensor networks - IPSN '07, 2007
    Co-Authors: Ram Kumar, Eddie Kohler, Mani Srivastava
    Abstract:

    Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware Memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a Memory protection system that prevents many forms of Memory corruption. We use software based fault isolation ("sandboxing") to restrict application Memory accesses and control flow to protection domains within the address space. A flexible and efficient Memory Map data structure records ownership and layout information for Memory regions; writes are validated using the Memory Map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected Memory region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand- boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented Memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.

Ram Kumar - One of the best experts on this subject based on the ideXlab platform.

  • a system for coarse grained Memory protection in tiny embedded processors
    Design Automation Conference, 2007
    Co-Authors: Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
    Abstract:

    Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of Memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides Memory protection in tiny embedded processors. . Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict Memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory Map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory Map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected Memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of Memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.

  • DAC - A system for coarse grained Memory protection in tiny embedded processors
    Proceedings of the 44th annual conference on Design automation - DAC '07, 2007
    Co-Authors: Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
    Abstract:

    Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of Memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides Memory protection in tiny embedded processors. . Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict Memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory Map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory Map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected Memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of Memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.

  • harbor software based Memory protection for sensor nodes
    Information Processing in Sensor Networks, 2007
    Co-Authors: Ram Kumar, Eddie Kohler, Mani Srivastava
    Abstract:

    Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware Memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a Memory protection system that prevents many forms of Memory corruption. We use software based fault isolation ("sandboxing") to restrict application Memory accesses and control flow to protection domains within the address space. A flexible and efficient Memory Map data structure records ownership and layout information for Memory regions; writes are validated using the Memory Map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected Memory region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand- boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented Memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.

  • IPSN - Harbor: software-based Memory protection for sensor nodes
    Proceedings of the 6th international conference on Information processing in sensor networks - IPSN '07, 2007
    Co-Authors: Ram Kumar, Eddie Kohler, Mani Srivastava
    Abstract:

    Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware Memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a Memory protection system that prevents many forms of Memory corruption. We use software based fault isolation ("sandboxing") to restrict application Memory accesses and control flow to protection domains within the address space. A flexible and efficient Memory Map data structure records ownership and layout information for Memory regions; writes are validated using the Memory Map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected Memory region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand- boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented Memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.

Eddie Kohler - One of the best experts on this subject based on the ideXlab platform.

  • a system for coarse grained Memory protection in tiny embedded processors
    Design Automation Conference, 2007
    Co-Authors: Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
    Abstract:

    Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of Memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides Memory protection in tiny embedded processors. . Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict Memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory Map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory Map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected Memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of Memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.

  • DAC - A system for coarse grained Memory protection in tiny embedded processors
    Proceedings of the 44th annual conference on Design automation - DAC '07, 2007
    Co-Authors: Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
    Abstract:

    Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of Memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides Memory protection in tiny embedded processors. . Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict Memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory Map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory Map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected Memory region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of Memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.

  • harbor software based Memory protection for sensor nodes
    Information Processing in Sensor Networks, 2007
    Co-Authors: Ram Kumar, Eddie Kohler, Mani Srivastava
    Abstract:

    Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware Memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a Memory protection system that prevents many forms of Memory corruption. We use software based fault isolation ("sandboxing") to restrict application Memory accesses and control flow to protection domains within the address space. A flexible and efficient Memory Map data structure records ownership and layout information for Memory regions; writes are validated using the Memory Map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected Memory region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand- boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented Memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.

  • IPSN - Harbor: software-based Memory protection for sensor nodes
    Proceedings of the 6th international conference on Information processing in sensor networks - IPSN '07, 2007
    Co-Authors: Ram Kumar, Eddie Kohler, Mani Srivastava
    Abstract:

    Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware Memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a Memory protection system that prevents many forms of Memory corruption. We use software based fault isolation ("sandboxing") to restrict application Memory accesses and control flow to protection domains within the address space. A flexible and efficient Memory Map data structure records ownership and layout information for Memory regions; writes are validated using the Memory Map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected Memory region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand- boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented Memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.

Maya Gokhale - One of the best experts on this subject based on the ideXlab platform.

  • DI-MMap—a scalable Memory-Map runtime for out-of-core data-intensive applications
    Cluster Computing, 2015
    Co-Authors: Brian Essen, Henry Hsieh, Sasha Ames, Roger Pearce, Maya Gokhale
    Abstract:

    We present DI-MMap, a high-performance runtime that Memory-Maps large external data sets into an application’s address space and shows significantly better performance than the Linux mMap system call. Our implementation is particularly effective when used with high performance locally attached Flash arrays on highly concurrent, latency-tolerant data-intensive HPC applications. We describe the kernel module and show performance results on a benchmark test suite, a new bioinformatics metagenomic classification application, and on a level-asynchronous Breadth-First Search (BFS) graph traversal algorithm. Using DI-MMap, the metagenomics classification application performs up to 4× better than standard Linux mMap . A fully external Memory configuration of BFS executes up to 7.44× faster than traditional mMap . Finally, we demonstrate that DI-MMap shows scalable out-of-core performance for BFS traversal in main Memory constrained scenarios. Such scalable Memory constrained performance would allow a system with a fixed amount of Memory to solve a larger problem as well as provide Memory QoS guarantees for systems running multiple data-intensive applications.

  • DI-MMap--a scalable Memory-Map runtime for out-of-core data-intensive applications
    Cluster Computing, 2013
    Co-Authors: Brian Van Essen, Henry Hsieh, Sasha Ames, Roger Pearce, Maya Gokhale
    Abstract:

    We present DI-MMap, a high-performance runtime that Memory-Maps large external data sets into an application's address space and shows significantly better performance than the Linux mMap system call. Our implementation is particularly effective when used with high performance locally attached Flash arrays on highly concurrent, latency-tolerant data-intensive HPC applications. We describe the kernel module and show performance results on a benchmark test suite, a new bioinformatics metagenomic classification application, and on a level-asynchronous Breadth-First Search (BFS) graph traversal algorithm. Using DI-MMap, the metagenomics classification application performs up to 4× better than standard Linux mMap. A fully external Memory configuration of BFS executes up to 7.44× faster than traditional mMap. Finally, we demonstrate that DI-MMap shows scalable out-of-core performance for BFS traversal in main Memory constrained scenarios. Such scalable Memory constrained performance would allow a system with a fixed amount of Memory to solve a larger problem as well as provide Memory QoS guarantees for systems running multiple data-intensive applications.

  • di mMap a high performance Memory Map runtime for data intensive applications
    IEEE International Conference on High Performance Computing Data and Analytics, 2012
    Co-Authors: Brian Van Essen, Henry Hsieh, Sasha Ames, Maya Gokhale
    Abstract:

    We present DI-MMap, a high-performance runtime that Memory-Maps large external data sets into an application's address space and shows significantly better performance than the Linux mMap system call. Our implementation is particularly effective when used with high performance locally attached Flash arrays on highly concurrent, latency-tolerant data-intensive HPC applications. We describe the kernel module and show performance results on a benchmark test suite and on a new bioinformatics metagenomic classification application. For the complex metagenomics classification application, DI-MMap performs up to 4.88× better than standard Linux mMap.

  • SC Companion - DI-MMap: A High Performance Memory-Map Runtime for Data-Intensive Applications
    2012 SC Companion: High Performance Computing Networking Storage and Analysis, 2012
    Co-Authors: Brian Van Essen, Henry Hsieh, Sasha Ames, Maya Gokhale
    Abstract:

    We present DI-MMap, a high-performance runtime that Memory-Maps large external data sets into an application's address space and shows significantly better performance than the Linux mMap system call. Our implementation is particularly effective when used with high performance locally attached Flash arrays on highly concurrent, latency-tolerant data-intensive HPC applications. We describe the kernel module and show performance results on a benchmark test suite and on a new bioinformatics metagenomic classification application. For the complex metagenomics classification application, DI-MMap performs up to 4.88× better than standard Linux mMap.

Eduardo De La Torre - One of the best experts on this subject based on the ideXlab platform.

  • ReConFig - Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs
    2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015
    Co-Authors: Alfonso Rodríguez, Juan Valverde, Eduardo De La Torre
    Abstract:

    ARTICo3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High Level Synthesis constraints. However, the replication of these modules can be decided at runtime to accelerate kernels by increasing the overall number of threads, add modular redundancy to increase fault tolerance, or any combination of the previous. An execution scheduler is used at kernel invocation to deliver the appropriate data transfers, optimizing Memory transactions, and sequencing or parallelizing execution according to the configuration specified by the resource manager of the architecture. The model of computation is compatible with the OpenCL kernel execution model, and Memory transfers and architecture are arranged to match the same optimization criteria as for kernel execution in GPU architectures but, differently to other approaches, with dynamic hardware execution support. In this paper, a novel design methodology for multithreaded hardware accelerators is presented. The proposed framework provides OpenCL compatibility by implementing a Memory model based on shared Memory between host and compute device, which removes the overhead imposed by data transferences at global Memory level, and local memories inside each accelerator, i.e. compute unit, which are connected to global Memory through optimized DMA links. These local memories provide unified access, i.e. a continuous Memory Map, from the host side, but are divided in a configurable number of independent banks (to increase available ports) from the processing elements side to fully exploit data-level parallelism. Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities.

  • Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs
    2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015
    Co-Authors: Alfonso Rodríguez, Juan Valverde, Eduardo De La Torre
    Abstract:

    ARTICo3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High Level Synthesis constraints. However, the replication of these modules can be decided at runtime to accelerate kernels by increasing the overall number of threads, add modular redundancy to increase fault tolerance, or any combination of the previous. An execution scheduler is used at kernel invocation to deliver the appropriate data transfers, optimizing Memory transactions, and sequencing or parallelizing execution according to the configuration specified by the resource manager of the architecture. The model of computation is compatible with the OpenCL kernel execution model, and Memory transfers and architecture are arranged to match the same optimization criteria as for kernel execution in GPU architectures but, differently to other approaches, with dynamic hardware execution support. In this paper, a novel design methodology for multithreaded hardware accelerators is presented. The proposed framework provides OpenCL compatibility by implementing a Memory model based on shared Memory between host and compute device, which removes the overhead imposed by data transferences at global Memory level, and local memories inside each accelerator, i.e. compute unit, which are connected to global Memory through optimized DMA links. These local memories provide unified access, i.e. a continuous Memory Map, from the host side, but are divided in a configurable number of independent banks (to increase available ports) from the processing elements side to fully exploit data-level parallelism. Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities.