The Experts below are selected from a list of 12 Experts worldwide ranked by ideXlab platform

Akira Yamawaki - One of the best experts on this subject based on the ideXlab platform.

  • Development of Memory Mapped Register and Bus Switch Circuit for Hardware Virtualization in GEDY
    Proceedings of The 6th IIAE International Conference on Intelligent Systems and Image Processing 2018, 2018
    Co-Authors: Sota Kono, Satoshi Yonemitsu, Akira Yamawaki
    Abstract:

    Truly general purpose microcomputers are difficult to develop. Because truly general purpose microcomputers have problems such as circuit scale, power consumption, unit price. GEDY (General purpose microcomputer with Dynamic partial reconfiguration) is the general purpose microcomputer architecture using dynamic partial reconfiguration of circuits. GEDY can deal with many embedded systems. Virtual GEDY has all peripheral devices. Developers writes the conventional microcomputer program that cooperates with the peripheral devices via the memory map. Physical GEDY realizes the function of virtual GEDY by dynamically partial reconfiguration the peripheral devices to the reconfiguration unit. For that purpose, the reconfiguration unit on physical GEDY needs to be virtualized. By virtualizing, programmers can write program without being conscious of circuit switching. This paper proposes memory mapped Register (MMR) and flexible bus switch (FBS) circuit. MMR and FBS are circuits for hardware virtualization in GEDY. Experimental results show that the proposed MMR and FBS enable operation with unified pin assignment.

Sota Kono - One of the best experts on this subject based on the ideXlab platform.

  • Development of Memory Mapped Register and Bus Switch Circuit for Hardware Virtualization in GEDY
    Proceedings of The 6th IIAE International Conference on Intelligent Systems and Image Processing 2018, 2018
    Co-Authors: Sota Kono, Satoshi Yonemitsu, Akira Yamawaki
    Abstract:

    Truly general purpose microcomputers are difficult to develop. Because truly general purpose microcomputers have problems such as circuit scale, power consumption, unit price. GEDY (General purpose microcomputer with Dynamic partial reconfiguration) is the general purpose microcomputer architecture using dynamic partial reconfiguration of circuits. GEDY can deal with many embedded systems. Virtual GEDY has all peripheral devices. Developers writes the conventional microcomputer program that cooperates with the peripheral devices via the memory map. Physical GEDY realizes the function of virtual GEDY by dynamically partial reconfiguration the peripheral devices to the reconfiguration unit. For that purpose, the reconfiguration unit on physical GEDY needs to be virtualized. By virtualizing, programmers can write program without being conscious of circuit switching. This paper proposes memory mapped Register (MMR) and flexible bus switch (FBS) circuit. MMR and FBS are circuits for hardware virtualization in GEDY. Experimental results show that the proposed MMR and FBS enable operation with unified pin assignment.

Prithvi Shankar - One of the best experts on this subject based on the ideXlab platform.

  • ISED - Method to Determine Contrariety between Architectures Containing Stratified Memory Mapped Register Sets
    2014 Fifth International Symposium on Electronic System Design, 2014
    Co-Authors: Vasant Easwaran, Nagendra Gulur, Sushaanth Srirangapathi, Mihir Mody, Rahul Gulati, Prashant Karandikar, Prithvi Shankar
    Abstract:

    As silicon architectures get more and more complex, the cost of development has scaled exponentially. IC design and embedded software are significant contributors to the overall cost of development. To enable cost effective solutions, the most commonly used approach is to define a platform with a family of devices to address different market segments. This approach will enable hardware and software reuse. The major impediment in this approach is the lack of any single metric to quantify the extent of compatibility across the family of devices. This paper presents a novel method for producing detailed summary to understand the degree of architecture incompatibility. This method uses machine-readable specifications created for family of devices and provides extensive Register, bit-field and enumeration level differences between the two architectures to articulate the effort involved for software development and migration. This method has been used to determine architecture incompatibility for a derivative device spun off from a platform device, and was found to be 34% incompatible.

Satoshi Yonemitsu - One of the best experts on this subject based on the ideXlab platform.

  • Development of Memory Mapped Register and Bus Switch Circuit for Hardware Virtualization in GEDY
    Proceedings of The 6th IIAE International Conference on Intelligent Systems and Image Processing 2018, 2018
    Co-Authors: Sota Kono, Satoshi Yonemitsu, Akira Yamawaki
    Abstract:

    Truly general purpose microcomputers are difficult to develop. Because truly general purpose microcomputers have problems such as circuit scale, power consumption, unit price. GEDY (General purpose microcomputer with Dynamic partial reconfiguration) is the general purpose microcomputer architecture using dynamic partial reconfiguration of circuits. GEDY can deal with many embedded systems. Virtual GEDY has all peripheral devices. Developers writes the conventional microcomputer program that cooperates with the peripheral devices via the memory map. Physical GEDY realizes the function of virtual GEDY by dynamically partial reconfiguration the peripheral devices to the reconfiguration unit. For that purpose, the reconfiguration unit on physical GEDY needs to be virtualized. By virtualizing, programmers can write program without being conscious of circuit switching. This paper proposes memory mapped Register (MMR) and flexible bus switch (FBS) circuit. MMR and FBS are circuits for hardware virtualization in GEDY. Experimental results show that the proposed MMR and FBS enable operation with unified pin assignment.

Vasant Easwaran - One of the best experts on this subject based on the ideXlab platform.

  • ISED - Method to Determine Contrariety between Architectures Containing Stratified Memory Mapped Register Sets
    2014 Fifth International Symposium on Electronic System Design, 2014
    Co-Authors: Vasant Easwaran, Nagendra Gulur, Sushaanth Srirangapathi, Mihir Mody, Rahul Gulati, Prashant Karandikar, Prithvi Shankar
    Abstract:

    As silicon architectures get more and more complex, the cost of development has scaled exponentially. IC design and embedded software are significant contributors to the overall cost of development. To enable cost effective solutions, the most commonly used approach is to define a platform with a family of devices to address different market segments. This approach will enable hardware and software reuse. The major impediment in this approach is the lack of any single metric to quantify the extent of compatibility across the family of devices. This paper presents a novel method for producing detailed summary to understand the degree of architecture incompatibility. This method uses machine-readable specifications created for family of devices and provides extensive Register, bit-field and enumeration level differences between the two architectures to articulate the effort involved for software development and migration. This method has been used to determine architecture incompatibility for a derivative device spun off from a platform device, and was found to be 34% incompatible.