The Experts below are selected from a list of 72 Experts worldwide ranked by ideXlab platform
Chengyong Wu - One of the best experts on this subject based on the ideXlab platform.
-
PACT - A software Memory Partition approach for eliminating bank-level interference in multicore systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12, 2012Co-Authors: Mingjie Xing, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them.
-
a software Memory Partition approach for eliminating bank level interference in multicore systems
International Conference on Parallel Architectures and Compilation Techniques, 2012Co-Authors: Mingjie Xing, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them.
-
A software Memory Partition approach for eliminating bank-level interference in multicore systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12, 2012Co-Authors: L E I Liu, ZEHAN CUI, Mingjie Xing, Yungang Bao, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them. This paper presents a practical software approach to effectively eliminate the interference without hardware modification. The key idea is to modify the OS Memory management subsystem to adopt a page-coloring based bank-level Partition mechanism (BPM), which allocates specific DRAM banks to specific cores (threads). By using BPM, Memory controllers can passively schedule Memory requests in a core-cluster (or thread-cluster) way. We implement BPM in Linux 2.6.32.15 kernel and evaluate BPM on 4-core and 8-core real machines by running randomly generated 20 multi-programmed workloads (each contains 4/8 benchmarks) and multi-threaded benchmark. Experimental results show that BPM can improve the overall system throughput by 4.7% on average (up to 8.6%), and reduce the maximum slowdown by 4.5% on average (up to 15.8%). Moreover, BPM also saves 5.2% of the energy consumption of Memory system.
Mingjie Xing - One of the best experts on this subject based on the ideXlab platform.
-
PACT - A software Memory Partition approach for eliminating bank-level interference in multicore systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12, 2012Co-Authors: Mingjie Xing, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them.
-
a software Memory Partition approach for eliminating bank level interference in multicore systems
International Conference on Parallel Architectures and Compilation Techniques, 2012Co-Authors: Mingjie Xing, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them.
-
A software Memory Partition approach for eliminating bank-level interference in multicore systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12, 2012Co-Authors: L E I Liu, ZEHAN CUI, Mingjie Xing, Yungang Bao, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them. This paper presents a practical software approach to effectively eliminate the interference without hardware modification. The key idea is to modify the OS Memory management subsystem to adopt a page-coloring based bank-level Partition mechanism (BPM), which allocates specific DRAM banks to specific cores (threads). By using BPM, Memory controllers can passively schedule Memory requests in a core-cluster (or thread-cluster) way. We implement BPM in Linux 2.6.32.15 kernel and evaluate BPM on 4-core and 8-core real machines by running randomly generated 20 multi-programmed workloads (each contains 4/8 benchmarks) and multi-threaded benchmark. Experimental results show that BPM can improve the overall system throughput by 4.7% on average (up to 8.6%), and reduce the maximum slowdown by 4.5% on average (up to 15.8%). Moreover, BPM also saves 5.2% of the energy consumption of Memory system.
Christian Engelmann - One of the best experts on this subject based on the ideXlab platform.
-
nvmalloc exposing an aggregate ssd store as a Memory Partition in extreme scale machines
International Parallel and Distributed Processing Symposium, 2012Co-Authors: Chao Wang, Sudharshan S Vazhkudai, Fei Meng, Christian EngelmannAbstract:DRAM is a precious resource in extreme-scale machines and is increasingly becoming scarce, mainly due to the growing number of cores per node. On future multi-peta flop and exa flop machines, the Memory pressure is likely to be so severe that we need to rethink our Memory usage models. Fortunately, the advent of non-volatile Memory (NVM) offers a unique opportunity in this space. Current NVM offerings possess several desirable properties, such as low cost and power efficiency, but suffer from high latency and lifetime issues. We need rich techniques to be able to use them alongside DRAM. In this paper, we propose a novel approach for exploiting NVM as a secondary Memory Partition so that applications can explicitly allocate and manipulate Memory regions therein. More specifically, we propose an NVMalloc library with a suite of services that enables applications to access a distributed NVM storage system. We have devised ways within NVMalloc so that the storage system, built from compute node-local NVM devices, can be accessed in a byte-addressable fashion using the Memory mapped I/O interface. Our approach has the potential to re-energize out-of-core computations on large-scale machines by having applications allocate certain variables through NVMalloc, thereby increasing the overall Memory capacity available. Our evaluation on a 128-core cluster shows that NVMalloc enables applications to compute problem sizes larger than the physical Memory in a cost-effective manner. It can bring more performance/efficiency gain with increased computation time between NVM Memory accesses or increased data access locality. In addition, our results suggest that while NVMalloc enables transparent access to NVM-resident variables, the explicit control it provides is crucial to optimize application performance.
-
IPDPS - NVMalloc: Exposing an Aggregate SSD Store as a Memory Partition in Extreme-Scale Machines
2012 IEEE 26th International Parallel and Distributed Processing Symposium, 2012Co-Authors: Chao Wang, Sudharshan S Vazhkudai, Fei Meng, Xiaosong Ma, Christian EngelmannAbstract:DRAM is a precious resource in extreme-scale machines and is increasingly becoming scarce, mainly due to the growing number of cores per node. On future multi-peta flop and exa flop machines, the Memory pressure is likely to be so severe that we need to rethink our Memory usage models. Fortunately, the advent of non-volatile Memory (NVM) offers a unique opportunity in this space. Current NVM offerings possess several desirable properties, such as low cost and power efficiency, but suffer from high latency and lifetime issues. We need rich techniques to be able to use them alongside DRAM. In this paper, we propose a novel approach for exploiting NVM as a secondary Memory Partition so that applications can explicitly allocate and manipulate Memory regions therein. More specifically, we propose an NVMalloc library with a suite of services that enables applications to access a distributed NVM storage system. We have devised ways within NVMalloc so that the storage system, built from compute node-local NVM devices, can be accessed in a byte-addressable fashion using the Memory mapped I/O interface. Our approach has the potential to re-energize out-of-core computations on large-scale machines by having applications allocate certain variables through NVMalloc, thereby increasing the overall Memory capacity available. Our evaluation on a 128-core cluster shows that NVMalloc enables applications to compute problem sizes larger than the physical Memory in a cost-effective manner. It can bring more performance/efficiency gain with increased computation time between NVM Memory accesses or increased data access locality. In addition, our results suggest that while NVMalloc enables transparent access to NVM-resident variables, the explicit control it provides is crucial to optimize application performance.
Mingyu Chen - One of the best experts on this subject based on the ideXlab platform.
-
PACT - A software Memory Partition approach for eliminating bank-level interference in multicore systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12, 2012Co-Authors: Mingjie Xing, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them.
-
a software Memory Partition approach for eliminating bank level interference in multicore systems
International Conference on Parallel Architectures and Compilation Techniques, 2012Co-Authors: Mingjie Xing, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them.
-
A software Memory Partition approach for eliminating bank-level interference in multicore systems
Proceedings of the 21st international conference on Parallel architectures and compilation techniques - PACT '12, 2012Co-Authors: L E I Liu, ZEHAN CUI, Mingjie Xing, Yungang Bao, Mingyu Chen, Chengyong WuAbstract:Main Memory system is a shared resource in modern multicore machines, resulting in serious interference, which causes performance degradation in terms of throughput slowdown and unfairness. Numerous new Memory scheduling algorithms have been proposed to address the interference problem. However, these algorithms usually employ complex scheduling logic and need hardware modification to Memory controllers, as a result, industrial venders seem to have some hesitation in adopting them. This paper presents a practical software approach to effectively eliminate the interference without hardware modification. The key idea is to modify the OS Memory management subsystem to adopt a page-coloring based bank-level Partition mechanism (BPM), which allocates specific DRAM banks to specific cores (threads). By using BPM, Memory controllers can passively schedule Memory requests in a core-cluster (or thread-cluster) way. We implement BPM in Linux 2.6.32.15 kernel and evaluate BPM on 4-core and 8-core real machines by running randomly generated 20 multi-programmed workloads (each contains 4/8 benchmarks) and multi-threaded benchmark. Experimental results show that BPM can improve the overall system throughput by 4.7% on average (up to 8.6%), and reduce the maximum slowdown by 4.5% on average (up to 15.8%). Moreover, BPM also saves 5.2% of the energy consumption of Memory system.
Chao Wang - One of the best experts on this subject based on the ideXlab platform.
-
nvmalloc exposing an aggregate ssd store as a Memory Partition in extreme scale machines
International Parallel and Distributed Processing Symposium, 2012Co-Authors: Chao Wang, Sudharshan S Vazhkudai, Fei Meng, Christian EngelmannAbstract:DRAM is a precious resource in extreme-scale machines and is increasingly becoming scarce, mainly due to the growing number of cores per node. On future multi-peta flop and exa flop machines, the Memory pressure is likely to be so severe that we need to rethink our Memory usage models. Fortunately, the advent of non-volatile Memory (NVM) offers a unique opportunity in this space. Current NVM offerings possess several desirable properties, such as low cost and power efficiency, but suffer from high latency and lifetime issues. We need rich techniques to be able to use them alongside DRAM. In this paper, we propose a novel approach for exploiting NVM as a secondary Memory Partition so that applications can explicitly allocate and manipulate Memory regions therein. More specifically, we propose an NVMalloc library with a suite of services that enables applications to access a distributed NVM storage system. We have devised ways within NVMalloc so that the storage system, built from compute node-local NVM devices, can be accessed in a byte-addressable fashion using the Memory mapped I/O interface. Our approach has the potential to re-energize out-of-core computations on large-scale machines by having applications allocate certain variables through NVMalloc, thereby increasing the overall Memory capacity available. Our evaluation on a 128-core cluster shows that NVMalloc enables applications to compute problem sizes larger than the physical Memory in a cost-effective manner. It can bring more performance/efficiency gain with increased computation time between NVM Memory accesses or increased data access locality. In addition, our results suggest that while NVMalloc enables transparent access to NVM-resident variables, the explicit control it provides is crucial to optimize application performance.
-
IPDPS - NVMalloc: Exposing an Aggregate SSD Store as a Memory Partition in Extreme-Scale Machines
2012 IEEE 26th International Parallel and Distributed Processing Symposium, 2012Co-Authors: Chao Wang, Sudharshan S Vazhkudai, Fei Meng, Xiaosong Ma, Christian EngelmannAbstract:DRAM is a precious resource in extreme-scale machines and is increasingly becoming scarce, mainly due to the growing number of cores per node. On future multi-peta flop and exa flop machines, the Memory pressure is likely to be so severe that we need to rethink our Memory usage models. Fortunately, the advent of non-volatile Memory (NVM) offers a unique opportunity in this space. Current NVM offerings possess several desirable properties, such as low cost and power efficiency, but suffer from high latency and lifetime issues. We need rich techniques to be able to use them alongside DRAM. In this paper, we propose a novel approach for exploiting NVM as a secondary Memory Partition so that applications can explicitly allocate and manipulate Memory regions therein. More specifically, we propose an NVMalloc library with a suite of services that enables applications to access a distributed NVM storage system. We have devised ways within NVMalloc so that the storage system, built from compute node-local NVM devices, can be accessed in a byte-addressable fashion using the Memory mapped I/O interface. Our approach has the potential to re-energize out-of-core computations on large-scale machines by having applications allocate certain variables through NVMalloc, thereby increasing the overall Memory capacity available. Our evaluation on a 128-core cluster shows that NVMalloc enables applications to compute problem sizes larger than the physical Memory in a cost-effective manner. It can bring more performance/efficiency gain with increased computation time between NVM Memory accesses or increased data access locality. In addition, our results suggest that while NVMalloc enables transparent access to NVM-resident variables, the explicit control it provides is crucial to optimize application performance.