The Experts below are selected from a list of 123 Experts worldwide ranked by ideXlab platform

Priya Chandran - One of the best experts on this subject based on the ideXlab platform.

  • dynamic partitioning of physical Memory among virtual machines asmi architectural support for Memory isolation
    ACM Symposium on Applied Computing, 2016
    Co-Authors: R Jithin, Priya Chandran
    Abstract:

    It is an open challenge for virtualization technology architects to provide security to Virtual Machine (VM), in the presence of an infected hypervisor, without much compromise on performance. A few hardware modifications have been introduced by manufactures like Intel and AMD to provide a secure VM environment with low performance degradation. These solutions are unable to provide VM isolation in the presence of an infected hypervisor. In this paper we propose a novel Memory architecture model, that can achieve a secure physical Memory Region to each VM without performance degradation.

  • dynamic partitioning of physical Memory among virtual machines asmi architectural support for Memory isolation
    arXiv: Hardware Architecture, 2015
    Co-Authors: R Jithin, Priya Chandran
    Abstract:

    Cloud computing relies on secure and efficient virtualization. Software level security solutions compromise the performance of virtual machines (VMs), as a large amount of computational power would be utilized for running the security modules. Moreover, software solutions are only as secure as the level that they work on. For example a security module on a hypervisor cannot provide security in the presence of an infected hypervisor. It is a challenge for virtualization technology architects to enhance the security of VMs without degrading their performance. Currently available server machines are not fully equipped to support a secure VM environment without compromising on performance. A few hardware modifications have been introduced by manufactures like Intel and AMD to provide a secure VM environment with low performance degradation. In this paper we propose a novel Memory architecture model named \textit{ Architectural Support for Memory Isolation(ASMI)}, that can achieve a true isolated physical Memory Region to each VM without degrading performance. Along with true Memory isolation, ASMI is designed to provide lower Memory access times, better utilization of available Memory, support for DMA isolation and support for platform independence for users of VMs.

R Jithin - One of the best experts on this subject based on the ideXlab platform.

  • dynamic partitioning of physical Memory among virtual machines asmi architectural support for Memory isolation
    ACM Symposium on Applied Computing, 2016
    Co-Authors: R Jithin, Priya Chandran
    Abstract:

    It is an open challenge for virtualization technology architects to provide security to Virtual Machine (VM), in the presence of an infected hypervisor, without much compromise on performance. A few hardware modifications have been introduced by manufactures like Intel and AMD to provide a secure VM environment with low performance degradation. These solutions are unable to provide VM isolation in the presence of an infected hypervisor. In this paper we propose a novel Memory architecture model, that can achieve a secure physical Memory Region to each VM without performance degradation.

  • dynamic partitioning of physical Memory among virtual machines asmi architectural support for Memory isolation
    arXiv: Hardware Architecture, 2015
    Co-Authors: R Jithin, Priya Chandran
    Abstract:

    Cloud computing relies on secure and efficient virtualization. Software level security solutions compromise the performance of virtual machines (VMs), as a large amount of computational power would be utilized for running the security modules. Moreover, software solutions are only as secure as the level that they work on. For example a security module on a hypervisor cannot provide security in the presence of an infected hypervisor. It is a challenge for virtualization technology architects to enhance the security of VMs without degrading their performance. Currently available server machines are not fully equipped to support a secure VM environment without compromising on performance. A few hardware modifications have been introduced by manufactures like Intel and AMD to provide a secure VM environment with low performance degradation. In this paper we propose a novel Memory architecture model named \textit{ Architectural Support for Memory Isolation(ASMI)}, that can achieve a true isolated physical Memory Region to each VM without degrading performance. Along with true Memory isolation, ASMI is designed to provide lower Memory access times, better utilization of available Memory, support for DMA isolation and support for platform independence for users of VMs.

Mani Srivastava - One of the best experts on this subject based on the ideXlab platform.

  • a system for coarse grained Memory protection in tiny embedded processors
    Design Automation Conference, 2007
    Co-Authors: Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
    Abstract:

    Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of Memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides Memory protection in tiny embedded processors. . Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict Memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected Memory Region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of Memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.

  • harbor software based Memory protection for sensor nodes
    Information Processing in Sensor Networks, 2007
    Co-Authors: Ram Kumar, Eddie Kohler, Mani Srivastava
    Abstract:

    Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware Memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a Memory protection system that prevents many forms of Memory corruption. We use software based fault isolation ("sandboxing") to restrict application Memory accesses and control flow to protection domains within the address space. A flexible and efficient Memory map data structure records ownership and layout information for Memory Regions; writes are validated using the Memory map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected Memory Region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand- boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented Memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.

Ram Kumar - One of the best experts on this subject based on the ideXlab platform.

  • a system for coarse grained Memory protection in tiny embedded processors
    Design Automation Conference, 2007
    Co-Authors: Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani Srivastava
    Abstract:

    Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no form of Memory protection. Programming errors in one application can easily corrupt the state of the operating system and other applications on the microcontroller. In this paper we propose a system that provides Memory protection in tiny embedded processors. . Our system consists of a software run-time working with minimal low-cost architectural extensions to the processor core that prevents corruption of state by buggy applications. We restrict Memory accesses and control flow of applications to protection domains within the address space. The software run-time consists of a Memory map: a flexible and efficient data structure that records ownership and layout information of the entire address space. Memory map checks are done for store instructions by hardware accelerators that significantly improve the performance of our system. We preserve control flow integrity by maintaining a Safe stack that stores return addresses in a protected Memory Region. Cross domain function calls are redirected through a software based jump table. Enhancements to the microcontroller call and return instructions use the jump table to track the current active domain. We have implemented our scheme on a VHDL model of ATMEGA103 microcontroller. Our evaluations show that embedded applications can enjoy the benefits of Memory protection with minimal impact on performance and a modest increase in the area of the microcontroller.

  • harbor software based Memory protection for sensor nodes
    Information Processing in Sensor Networks, 2007
    Co-Authors: Ram Kumar, Eddie Kohler, Mani Srivastava
    Abstract:

    Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no form of hardware Memory protection. Programming errors in one application can easily corrupt the state of the operating system or other applications. In this paper, we propose Harbor, a Memory protection system that prevents many forms of Memory corruption. We use software based fault isolation ("sandboxing") to restrict application Memory accesses and control flow to protection domains within the address space. A flexible and efficient Memory map data structure records ownership and layout information for Memory Regions; writes are validated using the Memory map. Control flow integrity is preserved by maintaining a safe stack that stores return addresses in a protected Memory Region. Run-time checks validate computed control flow instructions. Cross domain calls perform low-overhead control transfers between domains. Checks are introduced by rewriting an application's compiled binary. The sand- boxed result is verified on the sensor node before it is admitted for execution. Harbor's fault isolation properties depend only on the correctness of this verifier and the Harbor runtime. We have implemented and tested Harbor on the SOS operating system. Harbor detected and prevented Memory corruption caused by programming errors in application modules that had been in use for several months. Harbor's overhead, though high, is less than that of application-specific virtual machines, and reasonable for typical sensor workloads.

Rossow Christian - One of the best experts on this subject based on the ideXlab platform.

  • ret2spec: Speculative Execution Using Return Stack Buffers
    'Association for Computing Machinery (ACM)', 2018
    Co-Authors: Maisuradze Giorgi, Rossow Christian
    Abstract:

    Speculative execution is an optimization technique that has been part of CPUs for over a decade. It predicts the outcome and target of branch instructions to avoid stalling the execution pipeline. However, until recently, the security implications of speculative code execution have not been studied. In this paper, we investigate a special type of branch predictor that is responsible for predicting return addresses. To the best of our knowledge, we are the first to study return address predictors and their consequences for the security of modern software. In our work, we show how return stack buffers (RSBs), the core unit of return address predictors, can be used to trigger misspeculations. Based on this knowledge, we propose two new attack variants using RSBs that give attackers similar capabilities as the documented Spectre attacks. We show how local attackers can gain arbitrary speculative code execution across processes, e.g., to leak passwords another user enters on a shared system. Our evaluation showed that the recent Spectre countermeasures deployed in operating systems can also cover such RSB-based cross-process attacks. Yet we then demonstrate that attackers can trigger misspeculation in JIT environments in order to leak arbitrary Memory content of browser processes. Reading outside the sandboxed Memory Region with JIT-compiled code is still possible with 80\% accuracy on average.Comment: Updating to the cam-ready version and adding reference to the original pape

  • Ret2Spec: Speculative Execution Using Return Stack Buffers
    'Association for Computing Machinery (ACM)', 2018
    Co-Authors: Maisuradze Giorgi, Rossow Christian
    Abstract:

    Speculative execution is an optimization technique that has been part of CPUs for over a decade. It predicts the outcome and target of branch instructions to avoid stalling the execution pipeline. However, until recently, the security implications of speculative code execution have not been studied. In this paper, we investigate a special type of branch predictor that is responsible for predicting return addresses. To the best of our knowledge, we are the first to study return address predictors and their consequences for the security of modern software. In our work, we show how return stack buffers (RSBs), the core unit of return address predictors, can be used to trigger misspeculations. Based on this knowledge, we propose two new attack variants using RSBs that give attackers similar capabilities as the documented Spectre attacks. We show how local attackers can gain arbitrary speculative code execution across processes, e.g., to leak passwords another user enters on a shared system. Our evaluation showed that the recent Spectre countermeasures deployed in operating systems can also cover such RSB-based cross-process attacks. Yet we then demonstrate that attackers can trigger misspeculation in JIT environments in order to leak arbitrary Memory content of browser processes. Reading outside the sandboxed Memory Region with JIT-compiled code is still possible with 80% accuracy on average