The Experts below are selected from a list of 7131 Experts worldwide ranked by ideXlab platform
Felice Balarin - One of the best experts on this subject based on the ideXlab platform.
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Memory Subsystem simulation in software tlm t models
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Eric Cheung, Harry Hsieh, Felice BalarinAbstract:Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the Memory Subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in system-level design space exploration. In this paper, we present a novel technique to simulate Memory accesses in software TLM/T models. We use a compiler to automatically expose all Memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target Memory addresses for accurate cache and Memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on Memory Subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.
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ASP-DAC - Memory Subsystem simulation in software TLM/T models
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Eric Cheung, Harry Hsieh, Felice BalarinAbstract:Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the Memory Subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in system-level design space exploration. In this paper, we present a novel technique to simulate Memory accesses in software TLM/T models. We use a compiler to automatically expose all Memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target Memory addresses for accurate cache and Memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on Memory Subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.
Eric Cheung - One of the best experts on this subject based on the ideXlab platform.
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Memory Subsystem simulation in software tlm t models
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Eric Cheung, Harry Hsieh, Felice BalarinAbstract:Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the Memory Subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in system-level design space exploration. In this paper, we present a novel technique to simulate Memory accesses in software TLM/T models. We use a compiler to automatically expose all Memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target Memory addresses for accurate cache and Memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on Memory Subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.
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ASP-DAC - Memory Subsystem simulation in software TLM/T models
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Eric Cheung, Harry Hsieh, Felice BalarinAbstract:Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the Memory Subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in system-level design space exploration. In this paper, we present a novel technique to simulate Memory accesses in software TLM/T models. We use a compiler to automatically expose all Memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target Memory addresses for accurate cache and Memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on Memory Subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.
Harry Hsieh - One of the best experts on this subject based on the ideXlab platform.
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Memory Subsystem simulation in software tlm t models
Asia and South Pacific Design Automation Conference, 2009Co-Authors: Eric Cheung, Harry Hsieh, Felice BalarinAbstract:Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the Memory Subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in system-level design space exploration. In this paper, we present a novel technique to simulate Memory accesses in software TLM/T models. We use a compiler to automatically expose all Memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target Memory addresses for accurate cache and Memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on Memory Subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.
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ASP-DAC - Memory Subsystem simulation in software TLM/T models
2009 Asia and South Pacific Design Automation Conference, 2009Co-Authors: Eric Cheung, Harry Hsieh, Felice BalarinAbstract:Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since the Memory Subsystem accounts for up to 50% of the performance and energy expenditures, it has to be considered in system-level design space exploration. In this paper, we present a novel technique to simulate Memory accesses in software TLM/T models. We use a compiler to automatically expose all Memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target Memory addresses for accurate cache and Memory simulation. Simulating at more than 10MHz, our models allow realistic architectural design space explorations on Memory Subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.
Lizy K John - One of the best experts on this subject based on the ideXlab platform.
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a bandwidth aware Memory Subsystem resource management using non invasive resource profilers for large cmp systems
High-Performance Computer Architecture, 2010Co-Authors: Dimitris Kaseridis, Jeffrey A Stuecheli, Jian Chen, Lizy K JohnAbstract:By integrating multiple cores in a single chip, Chip Multiprocessors (CMP) provide an attractive approach to improve both system throughput and efficiency. This integration allows the sharing of on-chip resources which may lead to destructive interference between the executing workloads. MemorySubsystem is an important shared resource that contributes significantly to the overall throughput and power consumption. In order to prevent destructive interference, the cache capacity and Memory bandwidth requirements of the last level cache have to be controlled. While previously proposed schemes focus on resource sharing within a chip, we explore additional possibilities both inside and outside a single chip. We propose a dynamic Memory-Subsystem resource management scheme that considers both cache capacity and Memory bandwidth contention in large multi-chip CMP systems. Our approach uses low overhead, non-invasive resource profilers that are based on Mattson's stack distance algorithm to project each core's resource requirements and guide our cache partitioning algorithms. Our bandwidth-aware algorithm seeks for throughput optimizations among multiple chips by migrating workloads from the most resource-overcommitted chips to the ones with more available resources. Use of bandwidth as a criterion results in an overall 18% reduction in Memory bandwidth along with a 7.9% reduction in miss rate, compared to existing resource management schemes. Using a cycle-accurate full system simulator, our approach achieved an average improvement of 8.5% on throughput.
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HPCA - A bandwidth-aware Memory-Subsystem resource management using non-invasive resource profilers for large CMP systems
HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, 2010Co-Authors: Dimitris Kaseridis, Jeffrey A Stuecheli, Jian Chen, Lizy K JohnAbstract:By integrating multiple cores in a single chip, Chip Multiprocessors (CMP) provide an attractive approach to improve both system throughput and efficiency. This integration allows the sharing of on-chip resources which may lead to destructive interference between the executing workloads. MemorySubsystem is an important shared resource that contributes significantly to the overall throughput and power consumption. In order to prevent destructive interference, the cache capacity and Memory bandwidth requirements of the last level cache have to be controlled. While previously proposed schemes focus on resource sharing within a chip, we explore additional possibilities both inside and outside a single chip. We propose a dynamic Memory-Subsystem resource management scheme that considers both cache capacity and Memory bandwidth contention in large multi-chip CMP systems. Our approach uses low overhead, non-invasive resource profilers that are based on Mattson's stack distance algorithm to project each core's resource requirements and guide our cache partitioning algorithms. Our bandwidth-aware algorithm seeks for throughput optimizations among multiple chips by migrating workloads from the most resource-overcommitted chips to the ones with more available resources. Use of bandwidth as a criterion results in an overall 18% reduction in Memory bandwidth along with a 7.9% reduction in miss rate, compared to existing resource management schemes. Using a cycle-accurate full system simulator, our approach achieved an average improvement of 8.5% on throughput.
Mads Dam - One of the best experts on this subject based on the ideXlab platform.
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trustworthy virtualization of the armv7 Memory Subsystem
Conference on Current Trends in Theory and Practice of Informatics, 2015Co-Authors: Hamed Nemati, Roberto Guanciale, Mads DamAbstract:In order to host a general purpose operating system, hypervisors need to virtualize the CPU Memory Subsystem. This entails dynami- cally changing MMU resources, in particular the page tables, to allow a hosted OS to reconfigure its own Memory. In this paper we present the verification of the isolation properties of a hypervisor design that uses direct paging. This virtualization approach allows to host commodity OSs without requiring either shadow data structures or specialized hardware support. Our verification targets a system consisting of a commodity CPU for embedded devices ARMv7, a hypervisor and an untrusted guest running Linux.The verification involves three steps: i Formalization of an ARMv7 CPU that includes the MMU, ii Formalization of a system behavior that includes the hypervisor and the untrusted guest iii Verification of the isolation properties. Formalization and proof are done in the HOL4 theorem prover, thus allowing to re-use the existing HOL4 ARMv7 model developed in Cambridge.
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SOFSEM - Trustworthy Virtualization of the ARMv7 Memory Subsystem
Lecture Notes in Computer Science, 2015Co-Authors: Hamed Nemati, Roberto Guanciale, Mads DamAbstract:In order to host a general purpose operating system, hypervisors need to virtualize the CPU Memory Subsystem. This entails dynami- cally changing MMU resources, in particular the page tables, to allow a hosted OS to reconfigure its own Memory. In this paper we present the verification of the isolation properties of a hypervisor design that uses direct paging. This virtualization approach allows to host commodity OSs without requiring either shadow data structures or specialized hardware support. Our verification targets a system consisting of a commodity CPU for embedded devices ARMv7, a hypervisor and an untrusted guest running Linux.The verification involves three steps: i Formalization of an ARMv7 CPU that includes the MMU, ii Formalization of a system behavior that includes the hypervisor and the untrusted guest iii Verification of the isolation properties. Formalization and proof are done in the HOL4 theorem prover, thus allowing to re-use the existing HOL4 ARMv7 model developed in Cambridge.