The Experts below are selected from a list of 108411 Experts worldwide ranked by ideXlab platform

Balakrishna Venkatrao - One of the best experts on this subject based on the ideXlab platform.

  • A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost
    Journal of Instruction-level Parallelism, 2005
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    Continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, place enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-eectively. This paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems’ Shade simulator simulating SPARC executables of eight integer and seven floating-point programs in the SPEC CPU2000 benchmark suite and five programs from the MediaBench suite, and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

  • IPCCC - The potential of compression to improve Memory System Performance, power consumption, and cost
    Conference Proceedings of the 2003 IEEE International Performance Computing and Communications Conference 2003., 2003
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    The continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, places enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-effectively. The paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems' simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

Nihar R. Mahapatra - One of the best experts on this subject based on the ideXlab platform.

  • A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost
    Journal of Instruction-level Parallelism, 2005
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    Continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, place enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-eectively. This paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems’ Shade simulator simulating SPARC executables of eight integer and seven floating-point programs in the SPEC CPU2000 benchmark suite and five programs from the MediaBench suite, and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

  • IPCCC - The potential of compression to improve Memory System Performance, power consumption, and cost
    Conference Proceedings of the 2003 IEEE International Performance Computing and Communications Conference 2003., 2003
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    The continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, places enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-effectively. The paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems' simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

Jiangjiang Liu - One of the best experts on this subject based on the ideXlab platform.

  • A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost
    Journal of Instruction-level Parallelism, 2005
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    Continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, place enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-eectively. This paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems’ Shade simulator simulating SPARC executables of eight integer and seven floating-point programs in the SPEC CPU2000 benchmark suite and five programs from the MediaBench suite, and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

  • IPCCC - The potential of compression to improve Memory System Performance, power consumption, and cost
    Conference Proceedings of the 2003 IEEE International Performance Computing and Communications Conference 2003., 2003
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    The continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, places enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-effectively. The paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems' simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

S. Dangeti - One of the best experts on this subject based on the ideXlab platform.

  • A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost
    Journal of Instruction-level Parallelism, 2005
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    Continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, place enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-eectively. This paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems’ Shade simulator simulating SPARC executables of eight integer and seven floating-point programs in the SPEC CPU2000 benchmark suite and five programs from the MediaBench suite, and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

  • IPCCC - The potential of compression to improve Memory System Performance, power consumption, and cost
    Conference Proceedings of the 2003 IEEE International Performance Computing and Communications Conference 2003., 2003
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    The continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, places enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-effectively. The paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems' simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

K. Sundaresan - One of the best experts on this subject based on the ideXlab platform.

  • A Limit Study on the Potential of Compression for Improving Memory System Performance, Power Consumption, and Cost
    Journal of Instruction-level Parallelism, 2005
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    Continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, place enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-eectively. This paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems’ Shade simulator simulating SPARC executables of eight integer and seven floating-point programs in the SPEC CPU2000 benchmark suite and five programs from the MediaBench suite, and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.

  • IPCCC - The potential of compression to improve Memory System Performance, power consumption, and cost
    Conference Proceedings of the 2003 IEEE International Performance Computing and Communications Conference 2003., 2003
    Co-Authors: Nihar R. Mahapatra, Jiangjiang Liu, K. Sundaresan, S. Dangeti, Balakrishna Venkatrao
    Abstract:

    The continuing exponential growth in processor Performance, combined with technology, architecture, and application trends, places enormous demands on the Memory System to allow information storage and exchange at a high-enough Performance (i.e., to provide low latency and high bandwidth access to large amounts of information), at low power, and cost-effectively. The paper comprehensively analyzes the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the Memory System and evaluates the potential of compression in improving Performance, power consumption, and cost of the Memory System. Traces obtained with Sun MicroSystems' simulator simulating SPARC executables of nine integer and six floating-point programs in the SPEC CPU2000 benchmark suite and analyzed using Markov entropy models, existing compression schemes, and CACTI 3.0 and SimplePower timing, power, and area models yield impressive results.