The Experts below are selected from a list of 348246 Experts worldwide ranked by ideXlab platform
Q S Gao - One of the best experts on this subject based on the ideXlab platform.
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the chinese remainder theorem and the prime Memory System
International Symposium on Computer Architecture, 1993Co-Authors: Q S GaoAbstract:As we know, the conflict problem is a very important problem in Memory System of super computer, there are two kinds of conflict-free Memory System approaches: skewing scheme approach and prime Memory System approach. Previously published prime Memory approaches are complex or wasting 1/p of the Memory space for filling the “holes” [17], where p is the number of Memory modules. In this paper, based on Chinese remainder theorem, we present a perfect prime Memory System which only need to find the d Mod p without wasting any Memory space and without computing the quotient.
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ISCA - The Chinese remainder theorem and the prime Memory System
Proceedings of the 20th annual international symposium on Computer architecture - ISCA '93, 1993Co-Authors: Q S GaoAbstract:As we know, the conflict problem is a very important problem in Memory System of super computer, there are two kinds of conflict-free Memory System approaches: skewing scheme approach and prime Memory System approach. Previously published prime Memory approaches are complex or wasting 1/p of the Memory space for filling the “holes” [17], where p is the number of Memory modules. In this paper, based on Chinese remainder theorem, we present a perfect prime Memory System which only need to find the d Mod p without wasting any Memory space and without computing the quotient.
Jong Won Park - One of the best experts on this subject based on the ideXlab platform.
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SIMD Computer Using 16 Processing Elements for Multi-Access Memory System
Advances in Intelligent and Soft Computing, 2012Co-Authors: Jea-hee Kim, Jong Won ParkAbstract:Improving the speed of image processing is in great demand according to spread of high definition visual media or massive images applications. A Single Instruction Multiple Data (SIMD) computer attached to a host computer can accelerate various image processing and massive data operations. Especially, MAMS (Multi-access Memory System) can not only reduce the access time of the Memory but also improve the cost and complexity for the large volume of data demanded in visual media applications. This paper presents implementation of simulator for image processing algorithms and speed comparison of an SIMD architectural multi-access Memory System, MAMS-PP16 which consists of MAMS and 16 processing elements (PEs), executed with MAMS-PP4 which consists of MAMS and 4 processing elements(PEs). The newly designed MAMS-PP16 has a 64 bits instruction format and application specific instruction sets. The result of performance analysis verifies performance improvement and the consistent response of MAMS-PP16 through the morphology filter operation in image processing algorithms, comparing with a CISC-based(Intel Processor) Serial Processor.
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Multiaccess Memory System for attached SIMD computer
IEEE Transactions on Computers, 2004Co-Authors: Jong Won ParkAbstract:In order to reduce the Memory access time for a Single-Instruction Multiple-Data stream (SIMD) computer with pq processing elements attached to a host computer, a multiaccess Memory System is proposed. The proposed Memory System supports simultaneous access to pq data elements within a 4-directional block (p /spl times/ q), a row (1 /spl times/ pq), a column (pq /spl times/ 1), a forward-diagonal, and a backward-diagonal subarray with a constant interval in an arbitrary position in an M /spl times/ N array of data elements, where the number of Memory modules, m, is a prime number greater than pq. For the simple and fast address calculation and routing circuit, the address differences between the pq addresses and the base address are arranged in ascending order according to the index numbers of m Memory modules from the index number of Memory module of the first element. The proposed multiaccess Memory System provides more subarray types and more constant intervals than the previous Memory Systems.
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An efficient buffer Memory System for subarray access
IEEE Transactions on Parallel and Distributed Systems, 2001Co-Authors: Jong Won ParkAbstract:Many current graphical display Systems utilize a buffer Memory System to contain a two-dimensional image array to be modified and displayed. In order to speed up the update of the buffer Memory System, it is required that the buffer Memory System accesses many image points within an image subarray in parallel. This paper proposes an efficient buffer Memory System for a fast and high-resolution graphical display System. The Memory System provides parallel accesses to pq image points within a block(p/spl times/q), a horizontal (1/spl times/pq), a vertical (pq/spl times/1), a forward-diagonal, or a backward-diagonal subarray in a two-dimensional image array, M/spl times/N, where the design parameters p and q are all powers of two. In the address calculation and routing circuit of the proposed buffer Memory System, the address differences of the five subarrays are prearranged according to the index numbers of Memory modules and stored in two static random access memories (SRAMs), so that the address differences are simply added to the base address to obtain the addresses according to the index numbers of Memory modules. In addition, for the fast address calculation, one single multiplication operation in the base address calculation is replaced by a SRAM access, so that the multiplication operation can be performed during the SRAM access for the address differences for the case when N is not a power of two. The address calculation and routing circuit proposed in this paper is improved in the hardware cost, the complexity of control, and the speed over the previous circuits.
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An efficient Memory System for the SIMD construction of a Gaussian pyramid
IEEE Transactions on Parallel and Distributed Systems, 1996Co-Authors: Jong Won Park, D.t. HarperAbstract:In this paper, a Memory System is introduced for the efficient construction of a Gaussian pyramid. The Memory System consists of an address calculating circuit, an address routing circuit, a Memory module selection circuit, and 2/sup n/+1 Memory modules. The Memory System provides parallel access to 2/sup n/ image points whose patterns are a block, a row or a column, where the interval of the column and the block is 1 and the interval of the row is 2/sup l/,l/spl ges/0. The performance of a generic SIMD (single-instruction multiple-data) processor using the proposed Memory System is compared with one using an interleaved Memory System for the construction of a Gaussian pyramid. The ratio of the time of the construction of level 2 and level 10 from the original image (level 0) of an SIMD processor with an interleaved Memory System to that of the proposed Memory System is 1.485 and 1.633, respectively.
Yukie Nagai - One of the best experts on this subject based on the ideXlab platform.
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ICANN (2) - A perceptual Memory System for affordance learning in humanoid robots
Lecture Notes in Computer Science, 2011Co-Authors: Marc Kammer, Marko Tscherepanow, Thomas Schäck, Yukie NagaiAbstract:Memory constitutes an essential cognitive capability of humans and animals. It allows them to act in very complex, non-stationary environments. In this paper, we propose a perceptual Memory System, which is intended to be applied on a humanoid robot learning affordances. According to the properties of biological Memory Systems, it has been designed in such a way as to enable life-long learning without catastrophic forgetting. Based on clustering sensory information, a symbolic representation is derived automatically. In contrast to alternative approaches, our Memory System does not rely on pre-trained models and works completely unsupervised.
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A Perceptual Memory System for Affordance Learning in Humanoid Robots
Artificial Neural Networks and Machine Learning – ICANN 2011, 2011Co-Authors: Marc Kammer, Marko Tscherepanow, Thomas Schäck, Yukie NagaiAbstract:Memory constitutes an essential cognitive capability of humans and animals. It allows them to act in very complex, non-stationary environments. In this paper, we propose a perceptual Memory System, which is intended to be applied on a humanoid robot learning affordances. According to the properties of biological Memory Systems, it has been designed in such a way as to enable life-long learning without catastrophic forgetting. Based on clustering sensory information, a symbolic representation is derived automatically. In contrast to alternative approaches, our Memory System does not rely on pre-trained models and works completely unsupervised.
R.m. Muir - One of the best experts on this subject based on the ideXlab platform.
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Memory System reliability improvement through associative cache redundancy
IEEE Journal of Solid-state Circuits, 1991Co-Authors: M.a. Lucente, C.h. Harris, R.m. MuirAbstract:The development of a VLSI device that provides Memory System self-testing and redundancy without incurring the overhead penalties of error-correction coding or page-swapping techniques is described. This device isolates hard errors in System Memory by writing a true and complement pattern to each System Memory location. Locations from an on-chip fully associative cache are then mapped into the address space in place of faulty locations. Since substitutions take place at the Memory word level, this method is more efficient than page swapping. Access to the onchip cache occurs in parallel with access to System Memory, so Memory access time is not increased, as it is with error detection and correction (EDAC). Analysis shows that this device can extend the mission time of a nonredundant Memory System by as much as 35 times. >
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Memory System reliability improvement through associative cache redundancy
IEEE Proceedings of the Custom Integrated Circuits Conference, 1Co-Authors: M.a. Lucente, C.h. Harris, R.m. MuirAbstract:A redundancy Memory architecture that increases System Memory reliability without incurring the Memory access speed degradation or size impact that result from using error-correction coding or paper-swapping techniques have been developed. The architecture uses a small associative cache Memory to provide redundant Memory locations. Logic is provided to perform Memory System testing and remapping of fault Memory locations. A VLSI circuit has been developed that incorporates the features of the architecture as a proof-of-concept demonstration. This device has been designated the Memory reliability enhancement peripheral (MREP). >
Marc Kammer - One of the best experts on this subject based on the ideXlab platform.
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ICANN (2) - A perceptual Memory System for affordance learning in humanoid robots
Lecture Notes in Computer Science, 2011Co-Authors: Marc Kammer, Marko Tscherepanow, Thomas Schäck, Yukie NagaiAbstract:Memory constitutes an essential cognitive capability of humans and animals. It allows them to act in very complex, non-stationary environments. In this paper, we propose a perceptual Memory System, which is intended to be applied on a humanoid robot learning affordances. According to the properties of biological Memory Systems, it has been designed in such a way as to enable life-long learning without catastrophic forgetting. Based on clustering sensory information, a symbolic representation is derived automatically. In contrast to alternative approaches, our Memory System does not rely on pre-trained models and works completely unsupervised.
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A Perceptual Memory System for Affordance Learning in Humanoid Robots
Artificial Neural Networks and Machine Learning – ICANN 2011, 2011Co-Authors: Marc Kammer, Marko Tscherepanow, Thomas Schäck, Yukie NagaiAbstract:Memory constitutes an essential cognitive capability of humans and animals. It allows them to act in very complex, non-stationary environments. In this paper, we propose a perceptual Memory System, which is intended to be applied on a humanoid robot learning affordances. According to the properties of biological Memory Systems, it has been designed in such a way as to enable life-long learning without catastrophic forgetting. Based on clustering sensory information, a symbolic representation is derived automatically. In contrast to alternative approaches, our Memory System does not rely on pre-trained models and works completely unsupervised.
