The Experts below are selected from a list of 22119 Experts worldwide ranked by ideXlab platform

Luca Benini - One of the best experts on this subject based on the ideXlab platform.

  • dory lightweight Memory hierarchy management for deep nn inference on iot endnodes work in progress
    International Conference on Hardware Software Codesign and System Synthesis, 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2x faster compared to its execution directly from L2 Memory while consuming 1.9x less energy.

  • Work-in-Progress: DORY: Lightweight Memory Hierarchy Management for Deep NN Inference on IoT Endnodes
    2019 International Conference on Hardware Software Codesign and System Synthesis (CODES+ISSS), 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2× faster compared to its execution directly from L2 Memory while consuming 1.9× less energy.

  • an adaptive data compression scheme for Memory Traffic minimization in processor based systems
    International Symposium on Circuits and Systems, 2002
    Co-Authors: Luca Benini, D Bruni, Alberto Macii, B Ricco, Enrico Macii
    Abstract:

    This paper proposes a data compression scheme for minimizing Memory Traffic in processor-based systems. Data compression and decompression are performed on-the-fly on the cache-to-Memory path, that is, uncompressed cache lines are compressed before they are written back to main Memory, and decompressed when cache refills take place. The distinguishing feature of the presented solution is its ability of providing high Memory Traffic reductions without requiring data profiling information. In other words, thanks to the self-learning mechanism it implements, the proposed scheme performs very closely to special-purpose compression approaches, whose main limitation is their inapplicability when off-line data profiling is not feasible. Memory Traffic reductions in the cache-to-Memory path of a core-based system running standard benchmark programs are, on average, around 34%, and are thus close to those achievable with profile-driven compression.

  • hardware assisted data compression for energy minimization in systems with embedded processors
    Design Automation and Test in Europe, 2002
    Co-Authors: Luca Benini, D Bruni, Alberto Macii, Enrico Macii
    Abstract:

    In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and efficient architecture for on-the-fly data compression and decompression whose field of operation is the cache-to-Memory path. Uncompressed cache lines are compressed before they are written back to main Memory, and decompressed when cache refills take place. We explore two classes of compression methods, profile-driven and differential, since they are characterized by compact HW implementations, and we compare their performance to those provided by some state-of-the-art compression methods (e.g., we have considered a few variants of the Lempel-Ziv encoder). We present experimental results about Memory Traffic and energy consumption in the cache-to-Memory path of a core-based system running standard benchmark programs. The achieved average energy savings range from 4.2% to 35.2%, depending on the selected compression algorithm.

Alessio Burrello - One of the best experts on this subject based on the ideXlab platform.

  • dory lightweight Memory hierarchy management for deep nn inference on iot endnodes work in progress
    International Conference on Hardware Software Codesign and System Synthesis, 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2x faster compared to its execution directly from L2 Memory while consuming 1.9x less energy.

  • Work-in-Progress: DORY: Lightweight Memory Hierarchy Management for Deep NN Inference on IoT Endnodes
    2019 International Conference on Hardware Software Codesign and System Synthesis (CODES+ISSS), 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2× faster compared to its execution directly from L2 Memory while consuming 1.9× less energy.

Davide Rossi - One of the best experts on this subject based on the ideXlab platform.

  • dory lightweight Memory hierarchy management for deep nn inference on iot endnodes work in progress
    International Conference on Hardware Software Codesign and System Synthesis, 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2x faster compared to its execution directly from L2 Memory while consuming 1.9x less energy.

  • Work-in-Progress: DORY: Lightweight Memory Hierarchy Management for Deep NN Inference on IoT Endnodes
    2019 International Conference on Hardware Software Codesign and System Synthesis (CODES+ISSS), 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2× faster compared to its execution directly from L2 Memory while consuming 1.9× less energy.

Francesco Conti - One of the best experts on this subject based on the ideXlab platform.

  • dory lightweight Memory hierarchy management for deep nn inference on iot endnodes work in progress
    International Conference on Hardware Software Codesign and System Synthesis, 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2x faster compared to its execution directly from L2 Memory while consuming 1.9x less energy.

  • Work-in-Progress: DORY: Lightweight Memory Hierarchy Management for Deep NN Inference on IoT Endnodes
    2019 International Conference on Hardware Software Codesign and System Synthesis (CODES+ISSS), 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2× faster compared to its execution directly from L2 Memory while consuming 1.9× less energy.

Angelo Garofalo - One of the best experts on this subject based on the ideXlab platform.

  • dory lightweight Memory hierarchy management for deep nn inference on iot endnodes work in progress
    International Conference on Hardware Software Codesign and System Synthesis, 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2x faster compared to its execution directly from L2 Memory while consuming 1.9x less energy.

  • Work-in-Progress: DORY: Lightweight Memory Hierarchy Management for Deep NN Inference on IoT Endnodes
    2019 International Conference on Hardware Software Codesign and System Synthesis (CODES+ISSS), 2019
    Co-Authors: Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini
    Abstract:

    IoT endnodes often couple a small and fast L1 scratchpad Memory with higher-capacity but lower bandwidth and speed L2 background Memory. The absence of a coherent hardware cache hierarchy saves energy but comes at the cost of labor-intensive explicit Memory management, complicating the deployment of algorithms with large data Memory footprint, such as Deep Neural Network (DNN) inference. In this work, we present DORY, a lightweight software-cache dedicated to DNN Deployment Oriented to Memory. DORY leverages static data tiling and DMA-based double buffering to hide the complexity of manual L1-L2 Memory Traffic management. DORY enables storage of activations and weights in L2 with less than 4% performance overhead with respect to direct execution in L1. We show that a 142 kB DNN achieving 79.9% on CIFAR-10 runs 3.2× faster compared to its execution directly from L2 Memory while consuming 1.9× less energy.