The Experts below are selected from a list of 159 Experts worldwide ranked by ideXlab platform

Chen Chen - One of the best experts on this subject based on the ideXlab platform.

  • research on arrival integration method for point Merge system in tactical Operation
    Conference on Combinatorial Optimization and Applications, 2017
    Co-Authors: Xinglong Wang, Chen Chen
    Abstract:

    In this paper, a Point Merge arrival integration method of tactical Operation is introduced under current Communication, Navigation and Surveillance technologies. In present research, the multi-agent theory is used to build and stimulate the arrival integration system. Agents involved in point Merge Operation and action modules are designed to realize automatic trajectory generating, adjustment, sequencing and conflict detection. The architecture of point Merge Operation is obtained as well. In order to verify the method, historical ADS-B data is analyzed and the point Merge procedures are designed for single runway and two runway arrival separately for different verification. The outcome proves the correctness and efficiency of the method and demonstrates the advantage of Point Merge procedure on reducing flight time, fuel consumption, delay time and ATC workload.

  • COCOA (1) - Research on Arrival Integration Method for Point Merge System in Tactical Operation
    Combinatorial Optimization and Applications, 2017
    Co-Authors: Xinglong Wang, Chen Chen
    Abstract:

    In this paper, a Point Merge arrival integration method of tactical Operation is introduced under current Communication, Navigation and Surveillance technologies. In present research, the multi-agent theory is used to build and stimulate the arrival integration system. Agents involved in point Merge Operation and action modules are designed to realize automatic trajectory generating, adjustment, sequencing and conflict detection. The architecture of point Merge Operation is obtained as well. In order to verify the method, historical ADS-B data is analyzed and the point Merge procedures are designed for single runway and two runway arrival separately for different verification. The outcome proves the correctness and efficiency of the method and demonstrates the advantage of Point Merge procedure on reducing flight time, fuel consumption, delay time and ATC workload.

Xinglong Wang - One of the best experts on this subject based on the ideXlab platform.

  • research on arrival integration method for point Merge system in tactical Operation
    Conference on Combinatorial Optimization and Applications, 2017
    Co-Authors: Xinglong Wang, Chen Chen
    Abstract:

    In this paper, a Point Merge arrival integration method of tactical Operation is introduced under current Communication, Navigation and Surveillance technologies. In present research, the multi-agent theory is used to build and stimulate the arrival integration system. Agents involved in point Merge Operation and action modules are designed to realize automatic trajectory generating, adjustment, sequencing and conflict detection. The architecture of point Merge Operation is obtained as well. In order to verify the method, historical ADS-B data is analyzed and the point Merge procedures are designed for single runway and two runway arrival separately for different verification. The outcome proves the correctness and efficiency of the method and demonstrates the advantage of Point Merge procedure on reducing flight time, fuel consumption, delay time and ATC workload.

  • COCOA (1) - Research on Arrival Integration Method for Point Merge System in Tactical Operation
    Combinatorial Optimization and Applications, 2017
    Co-Authors: Xinglong Wang, Chen Chen
    Abstract:

    In this paper, a Point Merge arrival integration method of tactical Operation is introduced under current Communication, Navigation and Surveillance technologies. In present research, the multi-agent theory is used to build and stimulate the arrival integration system. Agents involved in point Merge Operation and action modules are designed to realize automatic trajectory generating, adjustment, sequencing and conflict detection. The architecture of point Merge Operation is obtained as well. In order to verify the method, historical ADS-B data is analyzed and the point Merge procedures are designed for single runway and two runway arrival separately for different verification. The outcome proves the correctness and efficiency of the method and demonstrates the advantage of Point Merge procedure on reducing flight time, fuel consumption, delay time and ATC workload.

Yi Wang - One of the best experts on this subject based on the ideXlab platform.

  • DATE - An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems
    2011 Design Automation & Test in Europe, 2011
    Co-Authors: Yi Wang, Zili Shao
    Abstract:

    NAND flash memory is widely used in embedded systems due to its non-volatility, shock resistance and high cell density. In recent years, various Flash Translation Layer (FTL) schemes (especially hybrid-level FTL schemes) have been proposed. Although these FTL schemes provide good solutions in terms of endurance and wear-leveling, none of them have considered to reuse free pages in both data blocks and log blocks during a Merge Operation. By reusing these free pages, less free blocks are needed and the endurance of NAND flash memory is enhanced. We evaluate our reuse strategy using a variety of application specific I/O traces from Windows systems. Experimental results show that the proposed scheme can effectively reduce the erase counts and enhance the endurance of flash memory.

  • rnftl a reuse aware nand flash translation layer for flash memory
    Languages Compilers and Tools for Embedded Systems, 2010
    Co-Authors: Yi Wang, Meng Wang, Zili Shao, Yong Guan
    Abstract:

    In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our basic idea is to prevent a primary block with many free pages from being erased in a Merge Operation. The preserved primary blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts for each block in NAND flash can be enhanced. To the best of our knowledge, this is the first work to employ a reuse-aware strategy in FTL for improving the space utilization and endurance of NAND flash. We conduct experiments on a set of traces that collected from real workload in daily life. The experimental results show that our technique has significant improvement on space utilization, block lifetime and wear-leveling compared with the previous work.

  • LCTES - RNFTL: a reuse-aware NAND flash translation layer for flash memory
    Proceedings of the ACM SIGPLAN SIGBED 2010 conference on Languages compilers and tools for embedded systems - LCTES '10, 2010
    Co-Authors: Yi Wang, Meng Wang, Zili Shao, Yong Guan
    Abstract:

    In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our basic idea is to prevent a primary block with many free pages from being erased in a Merge Operation. The preserved primary blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts for each block in NAND flash can be enhanced. To the best of our knowledge, this is the first work to employ a reuse-aware strategy in FTL for improving the space utilization and endurance of NAND flash. We conduct experiments on a set of traces that collected from real workload in daily life. The experimental results show that our technique has significant improvement on space utilization, block lifetime and wear-leveling compared with the previous work.

Yong Guan - One of the best experts on this subject based on the ideXlab platform.

  • rnftl a reuse aware nand flash translation layer for flash memory
    Languages Compilers and Tools for Embedded Systems, 2010
    Co-Authors: Yi Wang, Meng Wang, Zili Shao, Yong Guan
    Abstract:

    In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our basic idea is to prevent a primary block with many free pages from being erased in a Merge Operation. The preserved primary blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts for each block in NAND flash can be enhanced. To the best of our knowledge, this is the first work to employ a reuse-aware strategy in FTL for improving the space utilization and endurance of NAND flash. We conduct experiments on a set of traces that collected from real workload in daily life. The experimental results show that our technique has significant improvement on space utilization, block lifetime and wear-leveling compared with the previous work.

  • LCTES - RNFTL: a reuse-aware NAND flash translation layer for flash memory
    Proceedings of the ACM SIGPLAN SIGBED 2010 conference on Languages compilers and tools for embedded systems - LCTES '10, 2010
    Co-Authors: Yi Wang, Meng Wang, Zili Shao, Yong Guan
    Abstract:

    In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our basic idea is to prevent a primary block with many free pages from being erased in a Merge Operation. The preserved primary blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts for each block in NAND flash can be enhanced. To the best of our knowledge, this is the first work to employ a reuse-aware strategy in FTL for improving the space utilization and endurance of NAND flash. We conduct experiments on a set of traces that collected from real workload in daily life. The experimental results show that our technique has significant improvement on space utilization, block lifetime and wear-leveling compared with the previous work.

Zili Shao - One of the best experts on this subject based on the ideXlab platform.

  • DATE - An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems
    2011 Design Automation & Test in Europe, 2011
    Co-Authors: Yi Wang, Zili Shao
    Abstract:

    NAND flash memory is widely used in embedded systems due to its non-volatility, shock resistance and high cell density. In recent years, various Flash Translation Layer (FTL) schemes (especially hybrid-level FTL schemes) have been proposed. Although these FTL schemes provide good solutions in terms of endurance and wear-leveling, none of them have considered to reuse free pages in both data blocks and log blocks during a Merge Operation. By reusing these free pages, less free blocks are needed and the endurance of NAND flash memory is enhanced. We evaluate our reuse strategy using a variety of application specific I/O traces from Windows systems. Experimental results show that the proposed scheme can effectively reduce the erase counts and enhance the endurance of flash memory.

  • rnftl a reuse aware nand flash translation layer for flash memory
    Languages Compilers and Tools for Embedded Systems, 2010
    Co-Authors: Yi Wang, Meng Wang, Zili Shao, Yong Guan
    Abstract:

    In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our basic idea is to prevent a primary block with many free pages from being erased in a Merge Operation. The preserved primary blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts for each block in NAND flash can be enhanced. To the best of our knowledge, this is the first work to employ a reuse-aware strategy in FTL for improving the space utilization and endurance of NAND flash. We conduct experiments on a set of traces that collected from real workload in daily life. The experimental results show that our technique has significant improvement on space utilization, block lifetime and wear-leveling compared with the previous work.

  • LCTES - RNFTL: a reuse-aware NAND flash translation layer for flash memory
    Proceedings of the ACM SIGPLAN SIGBED 2010 conference on Languages compilers and tools for embedded systems - LCTES '10, 2010
    Co-Authors: Yi Wang, Meng Wang, Zili Shao, Yong Guan
    Abstract:

    In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our basic idea is to prevent a primary block with many free pages from being erased in a Merge Operation. The preserved primary blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts for each block in NAND flash can be enhanced. To the best of our knowledge, this is the first work to employ a reuse-aware strategy in FTL for improving the space utilization and endurance of NAND flash. We conduct experiments on a set of traces that collected from real workload in daily life. The experimental results show that our technique has significant improvement on space utilization, block lifetime and wear-leveling compared with the previous work.