The Experts below are selected from a list of 26319 Experts worldwide ranked by ideXlab platform
Antonio Gonzalez - One of the best experts on this subject based on the ideXlab platform.
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CGO - Heterogeneous Clustered VLIW Microarchitectures
International Symposium on Code Generation and Optimization (CGO'07), 2007Co-Authors: Alex Aletà, Josep Maria Codina, Antonio Gonzalez, David KaeliAbstract:Increasing performance, while at the same time reducing power consumption, is a major design tradeoff in current microprocessors. In this paper, we investigate the potential of using a heterogeneous clustered VLIW microarchitecture. In the proposed microarchitecture, each cluster, the interconnection network and the supporting memory hierarchy can run at different frequencies and voltages. Some of the clusters can then be configured to be performanceoriented and run at high frequency, while the other clusters can be configured to be low-power-oriented and run at lower frequencies, thus reducing overall consumption. For this heterogeneous design to be effective, we need to select the most suitable frequencies and voltages for each component. We propose a scheme to choose these parameters based on a model that estimates the energy consumption and the execution time of floating-point codes at compile time. Finally, we present a modulo scheduling technique based on graph partitioning that exploits the opportunities presented on heterogeneous clustered Microarchitectures. Results show that the Energy-Delay2 product (ED2) can be significantly reduced by 15% on average for a microarchitecture with 4-clusters and by as much as 35% for selected programs.
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heterogeneous clustered vliw Microarchitectures
Symposium on Code Generation and Optimization, 2007Co-Authors: Alex Aletà, Josep Maria Codina, Antonio Gonzalez, David KaeliAbstract:Increasing performance, while at the same time reducing power consumption, is a major design tradeoff in current microprocessors. In this paper, we investigate the potential of using a heterogeneous clustered VLIW microarchitecture. In the proposed microarchitecture, each cluster, the interconnection network and the supporting memory hierarchy can run at different frequencies and voltages. Some of the clusters can then be configured to be performanceoriented and run at high frequency, while the other clusters can be configured to be low-power-oriented and run at lower frequencies, thus reducing overall consumption. For this heterogeneous design to be effective, we need to select the most suitable frequencies and voltages for each component. We propose a scheme to choose these parameters based on a model that estimates the energy consumption and the execution time of floating-point codes at compile time. Finally, we present a modulo scheduling technique based on graph partitioning that exploits the opportunities presented on heterogeneous clustered Microarchitectures. Results show that the Energy-Delay2 product (ED2) can be significantly reduced by 15% on average for a microarchitecture with 4-clusters and by as much as 35% for selected programs.
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IPDPS - Inherently workload-balanced clustered microarchitecture
19th IEEE International Parallel and Distributed Processing Symposium, 2005Co-Authors: Jaume Abella, Antonio GonzalezAbstract:The performance of clustered Microarchitectures relies on steering schemes that try to find the best trade-off between workload balance and inter-cluster communication penalties. In previously proposed clustered processors, reducing communication penalties and balancing the workload are opposite targets, since improving one usually implies a detriment in the other. In this paper we propose a new clustered microarchitecture that can minimize communication penalties without compromising workload balance. The key idea is to arrange the clusters in a ring topology in such a way that results of one cluster can be forwarded to the neighbor cluster with a very short latency. In this way, minimizing communication penalties is favored when the producer of a value and its consumer are placed in adjacent clusters, which also favors workload balance. The proposed microarchitecture is shown to outperform a state-of-the-art clustered processor. For instance, for an 8-cluster configuration and just one fully pipelined unidirectional bus, 15% speedup is achieved on average for FP programs.
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on chip interconnects and instruction steering schemes for clustered Microarchitectures
IEEE Transactions on Parallel and Distributed Systems, 2005Co-Authors: J.-m. Parcerisa, Antonio Gonzalez, J. Sahuquillo, J. DuatoAbstract:Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection networks for clustered superscalar Microarchitectures. This new class of interconnects has demands and characteristics different from traditional multiprocessor networks. In particular, in a clustered microarchitecture, a low intercluster communication latency is essential for high performance. We propose some point-to-point cluster interconnects and new improved instruction steering schemes. The results show that these point-to-point interconnects achieve much better performance than bus-based ones, and that the connectivity of the network together with effective steering schemes are key for high performance. We also show that these interconnects can be built with simple hardware and achieve a performance close to that of an idealized contention-free model.
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efficient interconnects for clustered Microarchitectures
International Conference on Parallel Architectures and Compilation Techniques, 2002Co-Authors: J.-m. Parcerisa, Antonio Gonzalez, J. Sahuquillo, J. DuatoAbstract:Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection networks for clustered Microarchitectures. This new class of interconnects has different demands and characteristics than traditional multiprocessor networks. In a clustered microarchitecture, a low inter-cluster communication latency is essential for high performance.We propose point-to-point interconnects together with an effective latency-aware instruction steering scheme and show that they achieve much better performance than bus-based interconnects. The results show that the connectivity of the network together with latency-aware steering schemes are key for high performance. We also show that these interconnects can be built with simple hardware and achieve a performance close to that of an idealized contention-free model.
David Kaeli - One of the best experts on this subject based on the ideXlab platform.
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CGO - Heterogeneous Clustered VLIW Microarchitectures
International Symposium on Code Generation and Optimization (CGO'07), 2007Co-Authors: Alex Aletà, Josep Maria Codina, Antonio Gonzalez, David KaeliAbstract:Increasing performance, while at the same time reducing power consumption, is a major design tradeoff in current microprocessors. In this paper, we investigate the potential of using a heterogeneous clustered VLIW microarchitecture. In the proposed microarchitecture, each cluster, the interconnection network and the supporting memory hierarchy can run at different frequencies and voltages. Some of the clusters can then be configured to be performanceoriented and run at high frequency, while the other clusters can be configured to be low-power-oriented and run at lower frequencies, thus reducing overall consumption. For this heterogeneous design to be effective, we need to select the most suitable frequencies and voltages for each component. We propose a scheme to choose these parameters based on a model that estimates the energy consumption and the execution time of floating-point codes at compile time. Finally, we present a modulo scheduling technique based on graph partitioning that exploits the opportunities presented on heterogeneous clustered Microarchitectures. Results show that the Energy-Delay2 product (ED2) can be significantly reduced by 15% on average for a microarchitecture with 4-clusters and by as much as 35% for selected programs.
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heterogeneous clustered vliw Microarchitectures
Symposium on Code Generation and Optimization, 2007Co-Authors: Alex Aletà, Josep Maria Codina, Antonio Gonzalez, David KaeliAbstract:Increasing performance, while at the same time reducing power consumption, is a major design tradeoff in current microprocessors. In this paper, we investigate the potential of using a heterogeneous clustered VLIW microarchitecture. In the proposed microarchitecture, each cluster, the interconnection network and the supporting memory hierarchy can run at different frequencies and voltages. Some of the clusters can then be configured to be performanceoriented and run at high frequency, while the other clusters can be configured to be low-power-oriented and run at lower frequencies, thus reducing overall consumption. For this heterogeneous design to be effective, we need to select the most suitable frequencies and voltages for each component. We propose a scheme to choose these parameters based on a model that estimates the energy consumption and the execution time of floating-point codes at compile time. Finally, we present a modulo scheduling technique based on graph partitioning that exploits the opportunities presented on heterogeneous clustered Microarchitectures. Results show that the Energy-Delay2 product (ED2) can be significantly reduced by 15% on average for a microarchitecture with 4-clusters and by as much as 35% for selected programs.
Jarkko Niiranen - One of the best experts on this subject based on the ideXlab platform.
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lattice structures as thermoelastic strain gradient metamaterials evidence from full field simulations and applications to functionally step wise graded beams
Composites Part B-engineering, 2019Co-Authors: Sergei Khakalo, Jarkko NiiranenAbstract:Abstract The present work investigates the mechanical and thermomechanical bending response of beam structures possessing a triangular lattice microarchitecture. The validity of generalized continuum models, in general, and the associated dimensionally reduced models for functionally step-wise-graded microarchitectural beams, in particular, is approved by full-field finite element simulations. Most importantly, the necessity of the temperature gradient in the Helmholtz free energy is substantiated. The corresponding strong and weak forms for the associated Bernoulli–Euler and Timoshenko models of functionally graded beams are derived. The effective classical thermoelastic properties of a metamaterial with a triangular lattice microarchitecture are defined by means of computational homogenization. The additional length scale parameter involved in the generalized beam models, and associated to the particular triangular microarchitecture, is calibrated by fitting the mechanical bending responses of a series of lattice beams to the analytical solutions of the corresponding theoretical models. Strongly size-dependent mechanical and size-independent thermal bending responses are observed for both thin and thick beams with triangular lattice Microarchitectures. Finally, different lattice beams with varying Microarchitectures are introduced and shown to behave as generalized functionally step-wise-graded beams with respect to the higher-order elastic modulus, i.e., the length scale parameter varying in the direction of the beam axis.
Jianlin Shi - One of the best experts on this subject based on the ideXlab platform.
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controlled construction of monodisperse la2 moo4 3 yb tm Microarchitectures with upconversion luminescent property
Journal of Physical Chemistry C, 2008Co-Authors: Zhenxing Chen, Na Zhang And, Jianlin ShiAbstract:Monodisperse La2(MoO4)3:Yb,Tm Microarchitectures with uniform waxberry-like morphology have been successfully constructed in large scale by a facile surfactant-assisted hydrothermal route, in which sodium lauryl sulfate (SLS) was used as the structure directing agent. It was found that the pH value was a crucial factor controlling the phase composition and purity, which was unaffected by surfactant SLS. The growth process of these waxberry-shaped Microarchitectures has been examined in detail, and it was proved that a special dissolution−recrystallization transformation mechanism as well as a preferential adsorption of SLS process was responsible for the morphology evolution of the La2(MoO4)3:Yb,Tm Microarchitectures. A mechanism for the formation of the waxberry-shape La2(MoO4)3:Yb,Tm Microarchitectures was put forward. The specially shaped architectures showed blue up-conversion emission properties.
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synthesis and characterization of uniform spindle shaped Microarchitectures self assembled from aligned single crystalline nanowires of lanthanum phosphates
Crystal Growth & Design, 2007Co-Authors: Lingxia Zhang, Hangrong Chen, Zile Hua, Jianlin ShiAbstract:A new synthetic approach using the Pluronic P123-assisted hydrothermal reaction of lanthanum phosphate and europium-doped lanthanum phosphate has been developed, which results in the formation of uniform spindle-shaped Microarchitectures most probably by a self-assembly process. Our results reveal that the obtained spindle-shaped Microarchitectures consist of several tens of aligned single-crystalline nanowires with smooth, well-defined facets and highly uniform morphologies. These well-defined spindle-shaped Microarchitectures show greatly enhanced photoluminescence in these compounds when compared to their counterparts of disordered arrangements. A possible formation mechanism for these spindle-shaped Microarchitectures is presented and discussed.
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controlled construction of uniform pompon shaped Microarchitectures self assembled from single crystalline lanthanum molybdate nanoflakes
Langmuir, 2007Co-Authors: Na Zhang, Hangrong Chen, Zile Hua, Jianlin ShiAbstract:Uniform three-dimensional La2(MoO4)3 nanostructures with a pompon shape have been successfully constructed by a simple surfactant-free hydrothermal approach via self-assembly from single-crystalline nanoflakes. The formation of the uniform pompon-shaped La2(MoO4)3 Microarchitectures is closely related to the presence of a proper amount of ammonium ions, and it is proposed that the pompon-shaped microarchitecture forms through an electrostatic attraction/repulsion effect between the oppositely charged flat surface and the edge of nanoflakes. Without the introduction of ammonium ions, no pompon-shaped Microarchitectures can be formed, and while under the presence of excess ammonium ions, the nanoflakes on the micropompons become amorphous, twisted, and rugged. The novel Microarchitectures of the product can be successfully modified from spherical to columelliform by using a mixed solvent of water/ethanol. This simple and efficient method may provide a practical reference to the controlled synthesis of other...
Alex Aletà - One of the best experts on this subject based on the ideXlab platform.
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CGO - Heterogeneous Clustered VLIW Microarchitectures
International Symposium on Code Generation and Optimization (CGO'07), 2007Co-Authors: Alex Aletà, Josep Maria Codina, Antonio Gonzalez, David KaeliAbstract:Increasing performance, while at the same time reducing power consumption, is a major design tradeoff in current microprocessors. In this paper, we investigate the potential of using a heterogeneous clustered VLIW microarchitecture. In the proposed microarchitecture, each cluster, the interconnection network and the supporting memory hierarchy can run at different frequencies and voltages. Some of the clusters can then be configured to be performanceoriented and run at high frequency, while the other clusters can be configured to be low-power-oriented and run at lower frequencies, thus reducing overall consumption. For this heterogeneous design to be effective, we need to select the most suitable frequencies and voltages for each component. We propose a scheme to choose these parameters based on a model that estimates the energy consumption and the execution time of floating-point codes at compile time. Finally, we present a modulo scheduling technique based on graph partitioning that exploits the opportunities presented on heterogeneous clustered Microarchitectures. Results show that the Energy-Delay2 product (ED2) can be significantly reduced by 15% on average for a microarchitecture with 4-clusters and by as much as 35% for selected programs.
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heterogeneous clustered vliw Microarchitectures
Symposium on Code Generation and Optimization, 2007Co-Authors: Alex Aletà, Josep Maria Codina, Antonio Gonzalez, David KaeliAbstract:Increasing performance, while at the same time reducing power consumption, is a major design tradeoff in current microprocessors. In this paper, we investigate the potential of using a heterogeneous clustered VLIW microarchitecture. In the proposed microarchitecture, each cluster, the interconnection network and the supporting memory hierarchy can run at different frequencies and voltages. Some of the clusters can then be configured to be performanceoriented and run at high frequency, while the other clusters can be configured to be low-power-oriented and run at lower frequencies, thus reducing overall consumption. For this heterogeneous design to be effective, we need to select the most suitable frequencies and voltages for each component. We propose a scheme to choose these parameters based on a model that estimates the energy consumption and the execution time of floating-point codes at compile time. Finally, we present a modulo scheduling technique based on graph partitioning that exploits the opportunities presented on heterogeneous clustered Microarchitectures. Results show that the Energy-Delay2 product (ED2) can be significantly reduced by 15% on average for a microarchitecture with 4-clusters and by as much as 35% for selected programs.
