The Experts below are selected from a list of 17310 Experts worldwide ranked by ideXlab platform
Walter Binder - One of the best experts on this subject based on the ideXlab platform.
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improving execution unit occupancy on smt based Processors through hardware aware thread scheduling
Future Generation Computer Systems, 2014Co-Authors: Achille Peternier, Danilo Ansaloni, Daniele Bonetta, Cesare Pautasso, Walter BinderAbstract:Modern Processor architectures are increasingly complex and heterogeneous, often requiring software solutions tailored to the specific hardware characteristics of each Processor model. In this article, we address this problem by targeting two Processors featuring Simultaneous MultiThreading (SMT) to improve the occupancy of their internal execution units through a sustained stream of instructions coming from more than one thread. We target the AMD Bulldozer and IBM POWER7?Processors as case studies for specific hardware-oriented performance optimizations that increase the variety of instructions sent to each core to maximize the occupancy of all its execution units. WorkOver, presented in this article, improves thread scheduling by increasing the performance of floating point-intensive workloads on Linux-based operating systems. WorkOver?is a user-space monitoring tool that automatically identifies FPU-intensive threads and schedules them in a more efficient way without requiring any patches or modifications at the kernel level. Our measurements using standard benchmark suites show that speedups of up to 20% can be achieved by simply allowing WorkOver?to monitor applications and schedule their threads, without any modification of the workload. We present WorkOver to improve thread-scheduling for better performance.We use performance counters to profile integer- and floating-point threads.Threads are scheduled according to hardware execution unit availability.WorkOver optimizes unit occupancy on AMD Bulldozer and IBM P7 Processors.We measured up to 20% speedup using Spec CPU and Scimark 2.0.
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hardware aware thread scheduling the case of asymmetric multicore Processors
International Conference on Parallel and Distributed Systems, 2012Co-Authors: Achille Peternier, Danilo Ansaloni, Daniele Bonetta, Cesare Pautasso, Walter BinderAbstract:Modern Processor architectures are increasingly complex and heterogeneous, often requiring solutions tailored to the specific characteristics of each Processor model. In this paper we address this problem by targeting the AMD Bulldozer Processor as case study for specific hardware-oriented performance optimizations. The Bulldozer architecture features an asymmetric simultaneous multithreading implementation with shared floating point units (FPUs) and per-core arithmetic logic units (ALUs). Bulld Over, presented in this paper, improves thread scheduling by exploiting this hardware characteristic to increase performance of floating point-intensive workloads on Linux-based operating systems. Bulld Over is a user-space monitoring tool that automatically identifies FPU-intensive threads and schedules them in a more efficient way without requiring any patches or modifications at the kernel level. Our measurements using standard benchmark suites show that speedups of up to 10% can be achieved by simply allowing Bulld Over to monitor applications, without any modification of the workload.
Tamer M Ozsu - One of the best experts on this subject based on the ideXlab platform.
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main memory hash joins on Modern Processor architectures
IEEE Transactions on Knowledge and Data Engineering, 2015Co-Authors: Cagri Balkesen, Jens Teubner, Gustavo Alonso, Tamer M OzsuAbstract:Existing main-memory hash join algorithms for multi-core can be classified into two camps. Hardware-oblivious hash join variants do not depend on hardware-specific parameters. Rather, they consider qualitative characteristics of Modern hardware and are expected to achieve good performance on any technologically similar platform. The assumption behind these algorithms is that hardware is now good enough at hiding its own limitations—through automatic hardware prefetching, out-of-order execution, or simultaneous multi-threading (SMT)—to make hardware-oblivious algorithms competitive without the overhead of carefully tuning to the underlying hardware. Hardware-conscious implementations, such as (parallel) radix join , aim to maximally exploit a given architecture by tuning the algorithm parameters (e.g., hash table sizes) to the particular features of the architecture. The assumption here is that explicit parameter tuning yields enough performance advantages to warrant the effort required. This paper compares the two approaches under a wide range of workloads (relative table sizes, tuple sizes, effects of sorted data, etc.) and configuration parameters (VM page sizes, number of threads, number of cores, SMT, SIMD, prefetching, etc.). The results show that hardware-conscious algorithms generally outperform hardware-oblivious ones. However, on specific workloads and special architectures with aggressive simultaneous multi-threading, hardware-oblivious algorithms are competitive. The main conclusion of the paper is that, in existing multi-core architectures, it is still important to carefully tailor algorithms to the underlying hardware to get the necessary performance. But Processor developments may require to revisit this conclusion in the future.
Achille Peternier - One of the best experts on this subject based on the ideXlab platform.
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improving execution unit occupancy on smt based Processors through hardware aware thread scheduling
Future Generation Computer Systems, 2014Co-Authors: Achille Peternier, Danilo Ansaloni, Daniele Bonetta, Cesare Pautasso, Walter BinderAbstract:Modern Processor architectures are increasingly complex and heterogeneous, often requiring software solutions tailored to the specific hardware characteristics of each Processor model. In this article, we address this problem by targeting two Processors featuring Simultaneous MultiThreading (SMT) to improve the occupancy of their internal execution units through a sustained stream of instructions coming from more than one thread. We target the AMD Bulldozer and IBM POWER7?Processors as case studies for specific hardware-oriented performance optimizations that increase the variety of instructions sent to each core to maximize the occupancy of all its execution units. WorkOver, presented in this article, improves thread scheduling by increasing the performance of floating point-intensive workloads on Linux-based operating systems. WorkOver?is a user-space monitoring tool that automatically identifies FPU-intensive threads and schedules them in a more efficient way without requiring any patches or modifications at the kernel level. Our measurements using standard benchmark suites show that speedups of up to 20% can be achieved by simply allowing WorkOver?to monitor applications and schedule their threads, without any modification of the workload. We present WorkOver to improve thread-scheduling for better performance.We use performance counters to profile integer- and floating-point threads.Threads are scheduled according to hardware execution unit availability.WorkOver optimizes unit occupancy on AMD Bulldozer and IBM P7 Processors.We measured up to 20% speedup using Spec CPU and Scimark 2.0.
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hardware aware thread scheduling the case of asymmetric multicore Processors
International Conference on Parallel and Distributed Systems, 2012Co-Authors: Achille Peternier, Danilo Ansaloni, Daniele Bonetta, Cesare Pautasso, Walter BinderAbstract:Modern Processor architectures are increasingly complex and heterogeneous, often requiring solutions tailored to the specific characteristics of each Processor model. In this paper we address this problem by targeting the AMD Bulldozer Processor as case study for specific hardware-oriented performance optimizations. The Bulldozer architecture features an asymmetric simultaneous multithreading implementation with shared floating point units (FPUs) and per-core arithmetic logic units (ALUs). Bulld Over, presented in this paper, improves thread scheduling by exploiting this hardware characteristic to increase performance of floating point-intensive workloads on Linux-based operating systems. Bulld Over is a user-space monitoring tool that automatically identifies FPU-intensive threads and schedules them in a more efficient way without requiring any patches or modifications at the kernel level. Our measurements using standard benchmark suites show that speedups of up to 10% can be achieved by simply allowing Bulld Over to monitor applications, without any modification of the workload.
A R Bishop - One of the best experts on this subject based on the ideXlab platform.
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a unified sparse matrix data format for efficient general sparse matrix vector multiplication on Modern Processors with wide simd units
SIAM Journal on Scientific Computing, 2014Co-Authors: Moritz Kreutzer, Georg Hager, Gerhard Wellein, H Fehske, A R BishopAbstract:Sparse matrix-vector multiplication (spMVM) is the most time-consuming kernel in many numerical algorithms and has been studied extensively on all Modern Processor and accelerator architectures. However, the optimal sparse matrix data storage format is highly hardware-specific, which could become an obstacle when using heterogeneous systems. Also, it is as yet unclear how the wide single instruction multiple data (SIMD) units in current multi- and many-core Processors should be used most efficiently if there is no structure in the sparsity pattern of the matrix. We suggest SELL-$C$-$\sigma$, a variant of Sliced ELLPACK, as a SIMD-friendly data format which combines long-standing ideas from general-purpose graphics processing units and vector computer programming. We discuss the advantages of SELL-$C$-$\sigma$ compared to established formats like Compressed Row Storage and ELLPACK and show its suitability on a variety of hardware platforms (Intel Sandy Bridge, Intel Xeon Phi, and Nvidia Tesla K20) for a wi...
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a unified sparse matrix data format for efficient general sparse matrix vector multiply on Modern Processors with wide simd units
arXiv: Mathematical Software, 2013Co-Authors: Moritz Kreutzer, Georg Hager, Gerhard Wellein, H Fehske, A R BishopAbstract:Sparse matrix-vector multiplication (spMVM) is the most time-consuming kernel in many numerical algorithms and has been studied extensively on all Modern Processor and accelerator architectures. However, the optimal sparse matrix data storage format is highly hardware-specific, which could become an obstacle when using heterogeneous systems. Also, it is as yet unclear how the wide single instruction multiple data (SIMD) units in current multi- and many-core Processors should be used most efficiently if there is no structure in the sparsity pattern of the matrix. We suggest SELL-C-sigma, a variant of Sliced ELLPACK, as a SIMD-friendly data format which combines long-standing ideas from General Purpose Graphics Processing Units (GPGPUs) and vector computer programming. We discuss the advantages of SELL-C-sigma compared to established formats like Compressed Row Storage (CRS) and ELLPACK and show its suitability on a variety of hardware platforms (Intel Sandy Bridge, Intel Xeon Phi and Nvidia Tesla K20) for a wide range of test matrices from different application areas. Using appropriate performance models we develop deep insight into the data transfer properties of the SELL-C-sigma spMVM kernel. SELL-C-sigma comes with two tuning parameters whose performance impact across the range of test matrices is studied and for which reasonable choices are proposed. This leads to a hardware-independent ("catch-all") sparse matrix format, which achieves very high efficiency for all test matrices across all hardware platforms.
Cagri Balkesen - One of the best experts on this subject based on the ideXlab platform.
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main memory hash joins on Modern Processor architectures
IEEE Transactions on Knowledge and Data Engineering, 2015Co-Authors: Cagri Balkesen, Jens Teubner, Gustavo Alonso, Tamer M OzsuAbstract:Existing main-memory hash join algorithms for multi-core can be classified into two camps. Hardware-oblivious hash join variants do not depend on hardware-specific parameters. Rather, they consider qualitative characteristics of Modern hardware and are expected to achieve good performance on any technologically similar platform. The assumption behind these algorithms is that hardware is now good enough at hiding its own limitations—through automatic hardware prefetching, out-of-order execution, or simultaneous multi-threading (SMT)—to make hardware-oblivious algorithms competitive without the overhead of carefully tuning to the underlying hardware. Hardware-conscious implementations, such as (parallel) radix join , aim to maximally exploit a given architecture by tuning the algorithm parameters (e.g., hash table sizes) to the particular features of the architecture. The assumption here is that explicit parameter tuning yields enough performance advantages to warrant the effort required. This paper compares the two approaches under a wide range of workloads (relative table sizes, tuple sizes, effects of sorted data, etc.) and configuration parameters (VM page sizes, number of threads, number of cores, SMT, SIMD, prefetching, etc.). The results show that hardware-conscious algorithms generally outperform hardware-oblivious ones. However, on specific workloads and special architectures with aggressive simultaneous multi-threading, hardware-oblivious algorithms are competitive. The main conclusion of the paper is that, in existing multi-core architectures, it is still important to carefully tailor algorithms to the underlying hardware to get the necessary performance. But Processor developments may require to revisit this conclusion in the future.