The Experts below are selected from a list of 84258 Experts worldwide ranked by ideXlab platform
M Hosseinzade - One of the best experts on this subject based on the ideXlab platform.
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new design of rns subtractor for Modulo 2 n 1
International Conference on Information and Communication Technologies, 2006Co-Authors: S. Timarchi, Kaivan Navi, M HosseinzadeAbstract:This paper presents a high-speed subtractor in residue number system (RNS). In this paper, utilizing the conversion of single range unsigned (SRU) number system to single range signed (SRS) number system, we have made the subtraction more rapidly. Moduli set of (2n - 1, 2n, 2n + 1) is very attractive and has so many advantages over the other moduli sets, when realizing the related circuits. Beside the arithmetic operation delays are restricted by Modulo 2n + 1. Therefore, this method especially for above moduli will be very useful. By this fact, n + 1 bit wide subtractors are reduced to n bit wide subtractor. It is shown that the proposed design delay is about n/(n + 1) percent of existing one. This property has lead to more efficient realization of VLSI aspects
Thomas Bitoun - One of the best experts on this subject based on the ideXlab platform.
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On the p-supports of a holonomic $$\mathcal {D}$$ D -module
Inventiones mathematicae, 2019Co-Authors: Thomas BitounAbstract:For a smooth variety Y over a perfect field of positive characteristic, the sheaf $$D_Y$$ D Y of crystalline differential operators on Y (also called the sheaf of PD -differential operators) is known to be an Azumaya algebra over $$T^*_{Y'},$$ T Y ′ ∗ , the cotangent space of the Frobenius twist $$Y'$$ Y ′ of Y . Thus to a sheaf of modules M over $$D_Y$$ D Y one can assign a closed subvariety of $$T^*_{Y'},$$ T Y ′ ∗ , called the p -support, namely the support of M seen as a sheaf on $$T^*_{Y'}.$$ T Y ′ ∗ . We study here the family of p -supports assigned to the reductions Modulo primes p of a holonomic $$\mathcal {D}$$ D -module. We prove that the Azumaya algebra of differential operators splits on the regular locus of the p -support and that the p -support is a Lagrangian subvariety of the cotangent space, for p large enough. The latter was conjectured by Kontsevich. Our approach also provides a new proof of the involutivity of the singular support of a holonomic $$\mathcal {D}$$ D -module, by reduction Modulo p .
Zhao Ya-qun - One of the best experts on this subject based on the ideXlab platform.
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Some properties of the dot product over the free module Z_m~n
Journal of Shandong University of Technology, 2003Co-Authors: Zhao Ya-qunAbstract:Discusses some properties of the dot product on the free module Z n m with rank n over the ring Z m of residue Modulo-m. With the dot product, a Z-module homomorphism η: E→Z m is defined, where E is a submodule of Z n m, kerη,E/kerη and some properties of η -1 are presented in the paper. And another Z-module homomorphism ρ:Z n m→Z k m(1kn) is also defined with the dot product, kerρ and Z n m/kerρ are given, corresponding properties of ρ -1 are discussed in the paper. In addition, the orthogonal submodule E ⊥ of E is defined by E ⊥={x∈Z n m|x·y=0,y∈E}, correlation properties of m-th root of unity u m over E are studied, and the formula (w∈Z n m)∑x∈Eu w·x m=|E|,w∈E ⊥, 0,w≠E ⊥. is obtained in the paper, which is very useful in the study of logical functions of cryptology.
G. Lakhani - One of the best experts on this subject based on the ideXlab platform.
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ICCD - VLSI design of Modulo adders/subtractors
Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors, 1Co-Authors: G. LakhaniAbstract:Elegant implementation of Modulo adders are presented. A design suitable for small moduli is given first, and then, by using the divide and conquer approach, a design for large moduli is derived. The designs are such that Modulo subtraction can also be performed on the same hardware. The designs are suitable for high-speed digital parallel processing. The propagation delay of a Modulo-64 adder realized using this design is 12 ns. >
Gopal Lakhaiii - One of the best experts on this subject based on the ideXlab platform.
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VLSI Design of Modulo Adders/Subtractors
1992Co-Authors: Gopal LakhaiiiAbstract:Thzs paper presents elegaiif zinplemeiitottzoiis of Modulo adders A design suzfablc for sinall moduli2 is given first and then by uszng the dwidc and conquer approach, a desigii for largt moduli? is derivcd TIIP dcszgns arc such thai Modulo sirbtracfion caii also be performed on flrt same hardirarc. Tlic desigiis arc suziablc for high-speed, digital signal. parallel processing. The propogaiion delay of a Modulo 64 adder rea1i:ed using this design zs 12 nanosec.
