The Experts below are selected from a list of 324 Experts worldwide ranked by ideXlab platform
Sri Raga Sudha Garimella - One of the best experts on this subject based on the ideXlab platform.
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Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), 2019Co-Authors: Lalitha Mohana Kalyani Garimella, Sri Raga Sudha GarimellaAbstract:Shrinking of process nodes is declining and demand is increasing for design perfection to optimize power, performance, area (PPA). Standard library cells (STD cells) being basic building blocks for ASIC/CPU design, play a key role in PPA enhancement and hence in design perfection. This paper presents first of its kind research to bridge the gap between conventional STD cell Monotonic characterization and resulted STD cell liberty format file (.lib file) attributes usage with respect to ASIC tool cost function in an ASIC/CPU design and proposes a novel 3 dimensional (3D) Monotonic characterization method for PPA boosting. An algorithm for characterizing 3D Monotonic cells is defined. About 10% to 60% of library cells are observed to be non-3D-Monotonic in various libraries, architecture of libraries, and technology of libraries. Primetime results proving that selecting 3D-Monotonic cells in an existing library using the algorithm give excellent PPA gain. By repairing non-3d-Monotonic cells to cells fitting 3D-Monotonic characterization, summary of post-route, post-extracted, primetime results from study of several projects showed further PPA improvement. PPA gain and advantages varies with ASIC flow settings, ASIC tool vendors, size of CPU, performance target, etc... No disadvantages are caused by using this algorithm.
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MWSCAS - Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), 2018Co-Authors: Lalitha Mohana Kalyani Garimella, Sri Raga Sudha GarimellaAbstract:Shrinking of process nodes is declining and demand is increasing for design perfection to optimize power, performance and area (PPA). Standard library cells (STD cells) being basic building blocks for ASIC/CPU design, they play a key role in PPA enhancement and in design perfection. This paper presents first of its kind research to bridge the gap between conventional STD cell Monotonic characterization and resulted STD cell liberty format file (.lib file) attributes usage with respect to ASIC tool cost function in an ASIC/CPU design and proposes a novel 3 dimensional (3D) Monotonic characterization method for PPA boosting. An Algorithm for characterizing 3D Monotonic cells is defined. About 10% to 60% of library cells are observed to be non-3D-Monotonic in various libraries, architecture of libraries, and technology of libraries. Primetime results proving that selecting 3D-Monotonic cells in an existing library using the algorithm give excellent PPA gain. By repairing non-3d-Monotonic cells to fit 3D-Monotonic characterization, and studying summary of post-route, post-extracted, primetime results from several projects showed further PPA improvement. PPA gain and advantages varies with ASIC flow settings, ASIC tool vendors, size of CPU, performance target, etc… There are no disadvantages are caused by the 3D-Monotonic characterization.
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Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018Co-Authors: Lalitha Mohana Kalyani Garimella, Sri Raga Sudha GarimellaAbstract:Shrinking of process nodes is declining and demand is increasing for design perfection to optimize power, performance and area (PPA). Standard library cells (STD cells) being basic building blocks for ASIC/CPU design, they play a key role in PPA enhancement and in design perfection. This paper presents first of its kind research to bridge the gap between conventional STD cell Monotonic characterization and resulted STD cell liberty format file (.lib file) attributes usage with respect to ASIC tool cost function in an ASIC/CPU design and proposes a novel 3 dimensional (3D) Monotonic characterization method for PPA boosting. An Algorithm for characterizing 3D Monotonic cells is defined. About 10% to 60% of library cells are observed to be non-3D-Monotonic in various libraries, architecture of libraries, and technology of libraries. Primetime results proving that selecting 3D-Monotonic cells in an existing library using the algorithm give excellent PPA gain. By repairing non-3d-Monotonic cells to fit 3D-Monotonic characterization, and studying summary of post-route, post-extracted, primetime results from several projects showed further PPA improvement. PPA gain and advantages varies with ASIC flow settings, ASIC tool vendors, size of CPU, performance target, etc... There are no disadvantages are caused by the 3D-Monotonic characterization.
Azer Bestavros - One of the best experts on this subject based on the ideXlab platform.
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statistical rate Monotonic scheduling
Real-Time Systems Symposium, 1998Co-Authors: Alia Atlas, Azer BestavrosAbstract:Statistical rate Monotonic scheduling (SRMS) is a generalization of the classical RMS results of C. Liu and J. Layland (1973) for periodic tasks with highly variable execution times and statistical QoS requirements. The main tenet of SRMS is that the variability in task resource requirements could be smoothed through aggregation to yield guaranteed QoS. This aggregation is done over time for a given task and across multiple tasks for a given period of time. Similar to RMS, SRMS has two components: a feasibility test and a scheduling algorithm. SRMS feasibility test ensures that it is possible for a given periodic task set to share a given resource without violating any of the statistical QoS constraints imposed on each task in the set. The SRMS scheduling algorithm consists of two parts: a job admission controller and a scheduler. The SRMS scheduler is a simple, preemptive, fixed priority scheduler. The SRMS job admission controller manages the QoS delivered to the various tasks through admit/reject and priority assignment decisions. In particular it ensures the important property of task isolation, whereby tasks do not infringe on each other.
Lalitha Mohana Kalyani Garimella - One of the best experts on this subject based on the ideXlab platform.
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Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), 2019Co-Authors: Lalitha Mohana Kalyani Garimella, Sri Raga Sudha GarimellaAbstract:Shrinking of process nodes is declining and demand is increasing for design perfection to optimize power, performance, area (PPA). Standard library cells (STD cells) being basic building blocks for ASIC/CPU design, play a key role in PPA enhancement and hence in design perfection. This paper presents first of its kind research to bridge the gap between conventional STD cell Monotonic characterization and resulted STD cell liberty format file (.lib file) attributes usage with respect to ASIC tool cost function in an ASIC/CPU design and proposes a novel 3 dimensional (3D) Monotonic characterization method for PPA boosting. An algorithm for characterizing 3D Monotonic cells is defined. About 10% to 60% of library cells are observed to be non-3D-Monotonic in various libraries, architecture of libraries, and technology of libraries. Primetime results proving that selecting 3D-Monotonic cells in an existing library using the algorithm give excellent PPA gain. By repairing non-3d-Monotonic cells to cells fitting 3D-Monotonic characterization, summary of post-route, post-extracted, primetime results from study of several projects showed further PPA improvement. PPA gain and advantages varies with ASIC flow settings, ASIC tool vendors, size of CPU, performance target, etc... No disadvantages are caused by using this algorithm.
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MWSCAS - Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), 2018Co-Authors: Lalitha Mohana Kalyani Garimella, Sri Raga Sudha GarimellaAbstract:Shrinking of process nodes is declining and demand is increasing for design perfection to optimize power, performance and area (PPA). Standard library cells (STD cells) being basic building blocks for ASIC/CPU design, they play a key role in PPA enhancement and in design perfection. This paper presents first of its kind research to bridge the gap between conventional STD cell Monotonic characterization and resulted STD cell liberty format file (.lib file) attributes usage with respect to ASIC tool cost function in an ASIC/CPU design and proposes a novel 3 dimensional (3D) Monotonic characterization method for PPA boosting. An Algorithm for characterizing 3D Monotonic cells is defined. About 10% to 60% of library cells are observed to be non-3D-Monotonic in various libraries, architecture of libraries, and technology of libraries. Primetime results proving that selecting 3D-Monotonic cells in an existing library using the algorithm give excellent PPA gain. By repairing non-3d-Monotonic cells to fit 3D-Monotonic characterization, and studying summary of post-route, post-extracted, primetime results from several projects showed further PPA improvement. PPA gain and advantages varies with ASIC flow settings, ASIC tool vendors, size of CPU, performance target, etc… There are no disadvantages are caused by the 3D-Monotonic characterization.
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Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow
2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018Co-Authors: Lalitha Mohana Kalyani Garimella, Sri Raga Sudha GarimellaAbstract:Shrinking of process nodes is declining and demand is increasing for design perfection to optimize power, performance and area (PPA). Standard library cells (STD cells) being basic building blocks for ASIC/CPU design, they play a key role in PPA enhancement and in design perfection. This paper presents first of its kind research to bridge the gap between conventional STD cell Monotonic characterization and resulted STD cell liberty format file (.lib file) attributes usage with respect to ASIC tool cost function in an ASIC/CPU design and proposes a novel 3 dimensional (3D) Monotonic characterization method for PPA boosting. An Algorithm for characterizing 3D Monotonic cells is defined. About 10% to 60% of library cells are observed to be non-3D-Monotonic in various libraries, architecture of libraries, and technology of libraries. Primetime results proving that selecting 3D-Monotonic cells in an existing library using the algorithm give excellent PPA gain. By repairing non-3d-Monotonic cells to fit 3D-Monotonic characterization, and studying summary of post-route, post-extracted, primetime results from several projects showed further PPA improvement. PPA gain and advantages varies with ASIC flow settings, ASIC tool vendors, size of CPU, performance target, etc... There are no disadvantages are caused by the 3D-Monotonic characterization.
Alia Atlas - One of the best experts on this subject based on the ideXlab platform.
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statistical rate Monotonic scheduling
Real-Time Systems Symposium, 1998Co-Authors: Alia Atlas, Azer BestavrosAbstract:Statistical rate Monotonic scheduling (SRMS) is a generalization of the classical RMS results of C. Liu and J. Layland (1973) for periodic tasks with highly variable execution times and statistical QoS requirements. The main tenet of SRMS is that the variability in task resource requirements could be smoothed through aggregation to yield guaranteed QoS. This aggregation is done over time for a given task and across multiple tasks for a given period of time. Similar to RMS, SRMS has two components: a feasibility test and a scheduling algorithm. SRMS feasibility test ensures that it is possible for a given periodic task set to share a given resource without violating any of the statistical QoS constraints imposed on each task in the set. The SRMS scheduling algorithm consists of two parts: a job admission controller and a scheduler. The SRMS scheduler is a simple, preemptive, fixed priority scheduler. The SRMS job admission controller manages the QoS delivered to the various tasks through admit/reject and priority assignment decisions. In particular it ensures the important property of task isolation, whereby tasks do not infringe on each other.
Yuhua Qian - One of the best experts on this subject based on the ideXlab platform.
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Fusing Complete Monotonic Decision Trees
IEEE Transactions on Knowledge and Data Engineering, 2017Co-Authors: Hang Xu, Wenjian Wang, Yuhua QianAbstract:Monotonic classification is a kind of classification task in which a Monotonicity constraint exist between features and class, i.e., if sample xi has a higher value in each feature than sample xj, it should be assigned to a class with a higher level than the level of xj's class. Several methods have been proposed, but they have some limits such as with limited kind of data or limited classification accuracy. In our former work, the classification accuracy on Monotonic classification has been improved by fusing Monotonic decision trees, but it always has a complex classification model. This work aims to find a Monotonic classifier to process both nominal and numeric data by fusing complete Monotonic decision trees. Through finding the completed feature subsets based on discernibility matrix on ordinal dataset, a set of Monotonic decision trees can be obtained directly and automatically, on which the rank is still preserved. Fewer decision trees are needed, which will serve as base classifiers to construct a decision forest fused complete Monotonic decision trees. The experiment results on 10 datasets demonstrate that the proposed method can reduce the number of base classifiers effectively and then simplify classification model, and obtain good classification performance simultaneously.
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Fusing Monotonic Decision Trees
IEEE Transactions on Knowledge and Data Engineering, 2015Co-Authors: Yuhua Qian, Hang Xu, Jiye Liang, Jieting WangAbstract:Ordinal classification with a Monotonicity constraint is a kind of classification tasks, in which the objects with better attribute values should not be assigned to a worse decision class. Several learning algorithms have been proposed to handle this kind of tasks in recent years. The rank entropy-based Monotonic decision tree is very representative thanks to its better robustness and generalization. Ensemble learning is an effective strategy to significantly improve the generalization ability of machine learning systems. The objective of this work is to develop a method of fusing Monotonic decision trees. In order to achieve this goal, we take two factors into account: attribute reduction and fusing principle. Through introducing variable dominance rough sets, we firstly propose an attribute reduction approach with rank-preservation for learning base classifiers, which can effectively avoid overfitting and improve classification performance. Then, we establish a fusing principe based on maximal probability through combining the base classifiers, which is used to further improve generalization ability of the learning system. The experimental analysis shows that the proposed fusing method can significantly improve classification performance of the learning system constructed by Monotonic decision trees.
