The Experts below are selected from a list of 3612 Experts worldwide ranked by ideXlab platform
Tang Wenjie - One of the best experts on this subject based on the ideXlab platform.
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a hierarchical parallel discrete event simulation kernel for Multicore Platform
Cluster Computing, 2013Co-Authors: Tang Wenjie, Yao Yiping, Zhu Wen-fengAbstract:The development of CPU has stepped into the era of Multicore. Current parallel simulation kernel utilizes Multicore resource by multi-process, which leads to inefficiency on communication and synchronization. To fulfill this gap, we proposed a HPSK (hierarchical parallel simulation kernel) model, which schedules logical processes and executes events in parallel with multithread paradigm. Based on this model, three key algorithms were proposed to support high performance: (1) An event management algorithm was proposed to improve the efficiency of creation and release of events. It uses a lock-free creation and asynchronous commitment mechanism to decouple the relationship between threads, hence reduce the overhead of locks. (2) A pointer-based communication algorithm was proposed to improve efficiency of communication between threads. It uses a buffer mechanism to avoid interrupting the execution of target thread. The target thread will read events from the buffers when it needs. By using ring-structure buffers, synchronization between sending and receiving of threads can be annihilated. (3) An approximate method was proposed to compute LBTS (Lower Bound on Time Stamp). It uses an asynchronous mechanism to eliminate disturbing of thread execution and a two-level filter mechanism to reduce redundant LBTS computation. A series of experiments with a modified phold model show that HPSK can achieve good performance for applications on different conditions. It can run 8× faster than μsik when event locality and lookahead is low.
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HSK: A Hierarchical Parallel Simulation Kernel for Multicore Platform
2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications, 2011Co-Authors: Tang WenjieAbstract:The development of CPU has stepped into the era of multi-core. Due to lack of support on thread level, most of the simulation Platform can not take full advantage of Multicore. To fulfill this gap, we proposed a hierarchical parallel simulation kernel(HSK) model. The model has two layers. The first layer, named process kernel, was responsible for managing all thread kernels on second layer. The second layer is a group of thread kernels, which were responsible for scheduling and advancing logical processes. Each thread kernel was mapped onto an executing thread to advance simulation parallel. In addition, two algorithms were proposed to support high performance: (1) To improve the communication efficiency between threads, we proposed a pointer-based communication mechanism. By using buffers, synchronization between threads can be annihilated. (2) To eliminate redundant Lower Bound on Time Stamp(LBTS) computation and not to interrupt thread execution, we employ an approximate method to compute LBTS asynchronously. A proof of validity was presented. The execution performance of HSK was demonstrated by a series of simulation experiments with a modified phold model. The HSK can achieve good speedup for applications, especially with coarse-grained event.
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ISPA - HSK: A Hierarchical Parallel Simulation Kernel for Multicore Platform
2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications, 2011Co-Authors: Tang WenjieAbstract:The development of CPU has stepped into the era of multi-core. Due to lack of support on thread level, most of the simulation Platform can not take full advantage of Multicore. To fulfill this gap, we proposed a hierarchical parallel simulation kernel(HSK) model. The model has two layers. The first layer, named process kernel, was responsible for managing all thread kernels on second layer. The second layer is a group of thread kernels, which were responsible for scheduling and advancing logical processes. Each thread kernel was mapped onto an executing thread to advance simulation parallel. In addition, two algorithms were proposed to support high performance: (1) To improve the communication efficiency between threads, we proposed a pointer-based communication mechanism. By using buffers, synchronization between threads can be annihilated. (2) To eliminate redundant Lower Bound on Time Stamp(LBTS) computation and not to interrupt thread execution, we employ an approximate method to compute LBTS asynchronously. A proof of validity was presented. The execution performance of HSK was demonstrated by a series of simulation experiments with a modified phold model. The HSK can achieve good speedup for applications, especially with coarse-grained event.
Haruo Yokota - One of the best experts on this subject based on the ideXlab platform.
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optimizing concurrent query execution on modern multisocket Multicore Platform
Symposium on Reliable Distributed Systems, 2014Co-Authors: Takeshi Mishima, Haruo YokotaAbstract:The upcoming generation of computer hardware brought several new challenges for underling software. The number of cores on a chip grows exponentially, allowing for an ever-increasing number of processes to execute in parallel. Therefore, how to efficiently utilize all of the concurrent processing ability provided by multi-core Platform becomes critical for achieving good system performances. We propose a CARIC-DA framework which optimizes the performance of DBMS on Multicore Platforms. Our middleware can improve the performance of the private cache levels by dispatching concurrent database queries to run on different processor cores according to the data needs of each query. Extensive experiments from microbenchmark to TPC-C benchmark have confirmed the effectiveness of CARIC-DA in improving the cache performance and providing higher throughput for DBMSs on modern AMD Multicore Platform. However, the Multicore Platforms are becoming more and more diverse and complex in recent years. Different manufactures are making different efforts to boost their performance by adopting different techniques. Therefore, it is important for software to be well turned according to the specific hardware features in order to fully take advantage of the target Multicore Platforms. In this paper, we analyzed the efficiency of our CARIC-DA framework on the modern Multicore Intel Platform. We compared the performance of different deployment strategies where we vary the mapping relationship between database processes and processor cores from Hyper-Threading enable to disable configurations. We evaluated the impact of CARIC-DA for different cache levels and for different query types on the Intel Multicore Platform.
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SRDS Workshops - Optimizing Concurrent Query Execution on Modern Multisocket Multicore Platform
2014 IEEE 33rd International Symposium on Reliable Distributed Systems Workshops, 2014Co-Authors: Takeshi Mishima, Haruo YokotaAbstract:The upcoming generation of computer hardware brought several new challenges for underling software. The number of cores on a chip grows exponentially, allowing for an ever-increasing number of processes to execute in parallel. Therefore, how to efficiently utilize all of the concurrent processing ability provided by multi-core Platform becomes critical for achieving good system performances. We propose a CARIC-DA framework which optimizes the performance of DBMS on Multicore Platforms. Our middleware can improve the performance of the private cache levels by dispatching concurrent database queries to run on different processor cores according to the data needs of each query. Extensive experiments from microbenchmark to TPC-C benchmark have confirmed the effectiveness of CARIC-DA in improving the cache performance and providing higher throughput for DBMSs on modern AMD Multicore Platform. However, the Multicore Platforms are becoming more and more diverse and complex in recent years. Different manufactures are making different efforts to boost their performance by adopting different techniques. Therefore, it is important for software to be well turned according to the specific hardware features in order to fully take advantage of the target Multicore Platforms. In this paper, we analyzed the efficiency of our CARIC-DA framework on the modern Multicore Intel Platform. We compared the performance of different deployment strategies where we vary the mapping relationship between database processes and processor cores from Hyper-Threading enable to disable configurations. We evaluated the impact of CARIC-DA for different cache levels and for different query types on the Intel Multicore Platform.
Takeshi Mishima - One of the best experts on this subject based on the ideXlab platform.
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optimizing concurrent query execution on modern multisocket Multicore Platform
Symposium on Reliable Distributed Systems, 2014Co-Authors: Takeshi Mishima, Haruo YokotaAbstract:The upcoming generation of computer hardware brought several new challenges for underling software. The number of cores on a chip grows exponentially, allowing for an ever-increasing number of processes to execute in parallel. Therefore, how to efficiently utilize all of the concurrent processing ability provided by multi-core Platform becomes critical for achieving good system performances. We propose a CARIC-DA framework which optimizes the performance of DBMS on Multicore Platforms. Our middleware can improve the performance of the private cache levels by dispatching concurrent database queries to run on different processor cores according to the data needs of each query. Extensive experiments from microbenchmark to TPC-C benchmark have confirmed the effectiveness of CARIC-DA in improving the cache performance and providing higher throughput for DBMSs on modern AMD Multicore Platform. However, the Multicore Platforms are becoming more and more diverse and complex in recent years. Different manufactures are making different efforts to boost their performance by adopting different techniques. Therefore, it is important for software to be well turned according to the specific hardware features in order to fully take advantage of the target Multicore Platforms. In this paper, we analyzed the efficiency of our CARIC-DA framework on the modern Multicore Intel Platform. We compared the performance of different deployment strategies where we vary the mapping relationship between database processes and processor cores from Hyper-Threading enable to disable configurations. We evaluated the impact of CARIC-DA for different cache levels and for different query types on the Intel Multicore Platform.
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SRDS Workshops - Optimizing Concurrent Query Execution on Modern Multisocket Multicore Platform
2014 IEEE 33rd International Symposium on Reliable Distributed Systems Workshops, 2014Co-Authors: Takeshi Mishima, Haruo YokotaAbstract:The upcoming generation of computer hardware brought several new challenges for underling software. The number of cores on a chip grows exponentially, allowing for an ever-increasing number of processes to execute in parallel. Therefore, how to efficiently utilize all of the concurrent processing ability provided by multi-core Platform becomes critical for achieving good system performances. We propose a CARIC-DA framework which optimizes the performance of DBMS on Multicore Platforms. Our middleware can improve the performance of the private cache levels by dispatching concurrent database queries to run on different processor cores according to the data needs of each query. Extensive experiments from microbenchmark to TPC-C benchmark have confirmed the effectiveness of CARIC-DA in improving the cache performance and providing higher throughput for DBMSs on modern AMD Multicore Platform. However, the Multicore Platforms are becoming more and more diverse and complex in recent years. Different manufactures are making different efforts to boost their performance by adopting different techniques. Therefore, it is important for software to be well turned according to the specific hardware features in order to fully take advantage of the target Multicore Platforms. In this paper, we analyzed the efficiency of our CARIC-DA framework on the modern Multicore Intel Platform. We compared the performance of different deployment strategies where we vary the mapping relationship between database processes and processor cores from Hyper-Threading enable to disable configurations. We evaluated the impact of CARIC-DA for different cache levels and for different query types on the Intel Multicore Platform.
Yuanzhen Cui - One of the best experts on this subject based on the ideXlab platform.
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accelerating the parallelization of lattice boltzmann method by exploiting the temporal locality
Ubiquitous Computing, 2017Co-Authors: Song Liu, Nianjun Zou, Yuanzhen CuiAbstract:The lattice Boltzmann method (LBM) is a widely used solution for the computational fluid dynamics. It has the natural advantages of parallelization that several parallelizable nested loops in space dimensions are enclosed by the time steps. Most previous work focus on the DOALL parallelism and data reuse for cache optimization. This paper proposes an effective approach to accelerate the LBM computing by fully exploiting temporal locality on shared memory Multicore Platform. The approach uses loop transformations to obtain the implementation of D2Q9 model of LBM that achieves data reuses for cache in successive time steps and wave-front parallelism. Besides, a synchronization strategy based on POST/WAIT operations is presented to optimize the communication among parallel threads. On an Intel Multicore Platform, the implementation of the proposed approach outperformed the original parallel codes and a cache-based approach for different grid sizes, improving the performance by 11% and 9% on average, respectively.
Zhu Wen-feng - One of the best experts on this subject based on the ideXlab platform.
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a hierarchical parallel discrete event simulation kernel for Multicore Platform
Cluster Computing, 2013Co-Authors: Tang Wenjie, Yao Yiping, Zhu Wen-fengAbstract:The development of CPU has stepped into the era of Multicore. Current parallel simulation kernel utilizes Multicore resource by multi-process, which leads to inefficiency on communication and synchronization. To fulfill this gap, we proposed a HPSK (hierarchical parallel simulation kernel) model, which schedules logical processes and executes events in parallel with multithread paradigm. Based on this model, three key algorithms were proposed to support high performance: (1) An event management algorithm was proposed to improve the efficiency of creation and release of events. It uses a lock-free creation and asynchronous commitment mechanism to decouple the relationship between threads, hence reduce the overhead of locks. (2) A pointer-based communication algorithm was proposed to improve efficiency of communication between threads. It uses a buffer mechanism to avoid interrupting the execution of target thread. The target thread will read events from the buffers when it needs. By using ring-structure buffers, synchronization between sending and receiving of threads can be annihilated. (3) An approximate method was proposed to compute LBTS (Lower Bound on Time Stamp). It uses an asynchronous mechanism to eliminate disturbing of thread execution and a two-level filter mechanism to reduce redundant LBTS computation. A series of experiments with a modified phold model show that HPSK can achieve good performance for applications on different conditions. It can run 8× faster than μsik when event locality and lookahead is low.