The Experts below are selected from a list of 7302 Experts worldwide ranked by ideXlab platform
Sanjay Ranka - One of the best experts on this subject based on the ideXlab platform.
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optimized sparse cholesky factorization on hybrid Multicore architectures
Journal of Computational Science, 2018Co-Authors: Meng Tang, Mohamed Gadou, Steven C Rennich, Timothy A Davis, Sanjay RankaAbstract:Abstract We present techniques for supernodal sparse Cholesky factorization on a hybrid Multicore platform consisting of a Multicore CPU and GPU. The techniques are the subtree algorithm, pipelining and multithreading. The subtree algorithm [15] minimizes PCIe transmissions by storing an entire branch of the elimination tree in the GPU memory (the elimination tree is a tree data structure describing the workflow of the factorization), and also reduces the total kernel launch time by launching BLAS kernels in batches. The pipelining technique overlaps the execution of GPU kernels and PCIe data transfers. The multithreading technique [17] creates multiple threads for both the CPU and the GPU, to utilize concurrency of the elimination tree. Our experimental results on a platform consisting of an Intel Multicore Processor along with an Nvidia GPU indicate a significant improvement in performance and energy over CHOLMOD (SuiteSparse 4.5.3), a sparse algorithm, after these techniques are applied.
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a multithreaded algorithm for sparse cholesky factorization on hybrid Multicore architectures
International Conference on Conceptual Structures, 2017Co-Authors: Meng Tang, Mohamed Gadou, Sanjay RankaAbstract:Abstract We present a multithreaded method for supernodal sparse Cholesky factorization on a hybrid Multicore platform consisting of a Multicore CPU and GPU. Our algorithm can utilize concurrency at different levels of the elimination tree by using multiple threads in both the CPU and the GPU. The elimination tree is a tree data structure describing the workflow of the factorization. Our experiments results on a platform consisting of an Intel Multicore Processor along with an Nvidia GPU indicate a significant improvement in performance and energy over single-threaded supernodal algorithm.
Meng Tang - One of the best experts on this subject based on the ideXlab platform.
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optimized sparse cholesky factorization on hybrid Multicore architectures
Journal of Computational Science, 2018Co-Authors: Meng Tang, Mohamed Gadou, Steven C Rennich, Timothy A Davis, Sanjay RankaAbstract:Abstract We present techniques for supernodal sparse Cholesky factorization on a hybrid Multicore platform consisting of a Multicore CPU and GPU. The techniques are the subtree algorithm, pipelining and multithreading. The subtree algorithm [15] minimizes PCIe transmissions by storing an entire branch of the elimination tree in the GPU memory (the elimination tree is a tree data structure describing the workflow of the factorization), and also reduces the total kernel launch time by launching BLAS kernels in batches. The pipelining technique overlaps the execution of GPU kernels and PCIe data transfers. The multithreading technique [17] creates multiple threads for both the CPU and the GPU, to utilize concurrency of the elimination tree. Our experimental results on a platform consisting of an Intel Multicore Processor along with an Nvidia GPU indicate a significant improvement in performance and energy over CHOLMOD (SuiteSparse 4.5.3), a sparse algorithm, after these techniques are applied.
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a multithreaded algorithm for sparse cholesky factorization on hybrid Multicore architectures
International Conference on Conceptual Structures, 2017Co-Authors: Meng Tang, Mohamed Gadou, Sanjay RankaAbstract:Abstract We present a multithreaded method for supernodal sparse Cholesky factorization on a hybrid Multicore platform consisting of a Multicore CPU and GPU. Our algorithm can utilize concurrency at different levels of the elimination tree by using multiple threads in both the CPU and the GPU. The elimination tree is a tree data structure describing the workflow of the factorization. Our experiments results on a platform consisting of an Intel Multicore Processor along with an Nvidia GPU indicate a significant improvement in performance and energy over single-threaded supernodal algorithm.
Bahhwee Gwee - One of the best experts on this subject based on the ideXlab platform.
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high throughput and secure authentication encryption on asynchronous Multicore Processor for edge computing iot applications
International SoC Design Conference, 2020Co-Authors: Ali Akbar Pammu, Ne Kyaw Zwa Lwin, Kwensiong Chong, Bahhwee GweeAbstract:We describe an Authentication based Matrix-transformation cum Parallel-encryption (AMP-MP) implemented on an Asynchronous Multicore Processor to achieve a high throughput and yet secure Advanced Encryption Standard based on Counter with Chaining Mode (AES-CCM). Our AMP-MP is realized on an 8-bit asynchronous 9-core Processor fabricated based on 65nm CMOS process. The experimental results show that the throughput of the authentication is 13.54Gbps while the throughput for both authentication and encryption collectively is 8.32Gbps, which are $17\times$ and $70\times$ faster than the reported counterparty respectively. Based on power dissipation and EM SCA on our AMP-MP, the secret key is unrevealed at $5\times 10^{5}$ traces, which is $\sim 17\times$ more secured than the standard ASIC AES-CCM implementation.
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a high throughput and secure authentication encryption aes ccm algorithm on asynchronous Multicore Processor
IEEE Transactions on Information Forensics and Security, 2019Co-Authors: Ali Akbar Pammu, Ne Kyaw Zwa Lwin, Kwensiong Chong, Bahhwee GweeAbstract:We propose an authentication-based matrix-transformation cum parallel-encryption implemented on an asynchronous Multicore Processor (AMP-MP) to achieve a high throughput and yet secure advanced encryption standard based on counter with chaining mode (AES-CCM). There are four main features in our proposed AMP-MP. First, we employ the matrix multiplication in GF(28) computation to transform the 16 plaintexts into one plaintext, hence improving the authentication speed by $32\times $ collectively at the transmitter and receiver. Second, we reschedule the operations of three AES encryptions in three different cores such that their physical leakages are compensated and equalized, thus reducing the correlation of physical leakage with the processed data by $> 3\times $ . Third, the intermediate values of AES-CCM are propagated asynchronously between different cores to randomize the physical leakages with the processed data, and therefore further enhance the security of AES-CCM against the SCA by another $3\times $ . Fourth, we propose a key adjusting technique based on S-Box byte-key transformation to protect the key against pattern-based attack. Our proposed AMP-MP is realized on an 8-bit asynchronous 9-core Processor fabricated based on the 65 nm CMOS process. The experimental results show that the throughput of the authentication is 13.54 Gbps while the throughput for both authentication and encryption collectively is 8.32 Gbps, which are $17\times $ and $70\times $ faster than the reported counterparty, respectively. Based on power dissipation and EM SCA on our proposed AMP-MP, the secret key is unrevealed at $5\times 105$ traces, which is $\sim 17\times $ more secured than the standard ASIC AES-CCM implementation.
Mohamed Gadou - One of the best experts on this subject based on the ideXlab platform.
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optimized sparse cholesky factorization on hybrid Multicore architectures
Journal of Computational Science, 2018Co-Authors: Meng Tang, Mohamed Gadou, Steven C Rennich, Timothy A Davis, Sanjay RankaAbstract:Abstract We present techniques for supernodal sparse Cholesky factorization on a hybrid Multicore platform consisting of a Multicore CPU and GPU. The techniques are the subtree algorithm, pipelining and multithreading. The subtree algorithm [15] minimizes PCIe transmissions by storing an entire branch of the elimination tree in the GPU memory (the elimination tree is a tree data structure describing the workflow of the factorization), and also reduces the total kernel launch time by launching BLAS kernels in batches. The pipelining technique overlaps the execution of GPU kernels and PCIe data transfers. The multithreading technique [17] creates multiple threads for both the CPU and the GPU, to utilize concurrency of the elimination tree. Our experimental results on a platform consisting of an Intel Multicore Processor along with an Nvidia GPU indicate a significant improvement in performance and energy over CHOLMOD (SuiteSparse 4.5.3), a sparse algorithm, after these techniques are applied.
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a multithreaded algorithm for sparse cholesky factorization on hybrid Multicore architectures
International Conference on Conceptual Structures, 2017Co-Authors: Meng Tang, Mohamed Gadou, Sanjay RankaAbstract:Abstract We present a multithreaded method for supernodal sparse Cholesky factorization on a hybrid Multicore platform consisting of a Multicore CPU and GPU. Our algorithm can utilize concurrency at different levels of the elimination tree by using multiple threads in both the CPU and the GPU. The elimination tree is a tree data structure describing the workflow of the factorization. Our experiments results on a platform consisting of an Intel Multicore Processor along with an Nvidia GPU indicate a significant improvement in performance and energy over single-threaded supernodal algorithm.
Jim Alvesfoss - One of the best experts on this subject based on the ideXlab platform.
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a security review of the cell broadband engine Processor
Hawaii International Conference on System Sciences, 2010Co-Authors: Jessica Smith, Jim AlvesfossAbstract:The Cell Broadband Engine Processor is a Multicore Processor that provides high throughput for vector processing that is being considered for use in secure communication and data processing environments. Prior to its acceptance in these facilities, its security features and flaws must be fully explored. However, as a the Cell BE is a Multicore system composed of one "normal" core and 8 smaller, SIMD cores, the analysis is of a different order of difficulty than that of a single core Processor. This paper highlights some concerns seen in the Cell BE when considered from a security perspective and possible solutions to some of these security concerns.