The Experts below are selected from a list of 62388 Experts worldwide ranked by ideXlab platform

Jie Min Zhao - One of the best experts on this subject based on the ideXlab platform.

Jin-yup Hwang - One of the best experts on this subject based on the ideXlab platform.

  • VTC Fall - A Packet-by-Packet Scheduling Algorithm for Wireless Multimedia Systems
    2007 IEEE 66th Vehicular Technology Conference, 2007
    Co-Authors: Jinyoung Oh, Jin-yup Hwang
    Abstract:

    In this paper, we propose a packet-by-packet scheduling algorithm which grants priority to each packet instead of a user. The proposed scheduler classifies packets inside of each user into three classes such as emergency, near emergency, and non-emergency packets based on packet delay ratio, and applies different scheduling schemes to grant priority in each region respectively. It can be possible to manage packets more efficiently for guaranteeing various Quality of Services (QoS) in wireless Multimedia Systems. Simulation results show that the proposed scheme offers higher system throughput and lower packet drop rate than other scheduling algorithms.

Liang-gee Chen - One of the best experts on this subject based on the ideXlab platform.

  • Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems
    Journal of VLSI signal processing systems for signal image and video technology, 2005
    Co-Authors: Po-chih Tseng, Chao-tsung Huang, Liang-gee Chen
    Abstract:

    In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation Multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable Multimedia Systems.

  • Reconfigurable discrete wavelet transform architecture for advanced Multimedia Systems
    2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682), 1
    Co-Authors: Po-chih Tseng, Chao-tsung Huang, Liang-gee Chen
    Abstract:

    A novel reconfigurable discrete wavelet transform architecture is proposed to meet the diverse computing requirements of advanced Multimedia Systems. The proposed architecture mainly consists of a reconfigurable processing element array and a reconfigurable address generator, featuring a dynamically reconfigurable capability where the wavelet filter kernels and wavelet decomposition structures can be reconfigured at run-time with little overhead. The lifting-based reconfigurable processing element array possesses better computational efficiency than a convolution-based architecture, and a systematic design method is provided to generate the hardware configurations of different wavelet filter kernels for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by the TSMC 0.35 /spl mu/m 1P4M CMOS process, and, at 50 MHz, it can achieve at most 100 Mpixel/sec transform throughput, proving it to be a universal and extremely flexible computing engine for advanced Multimedia Systems.

Qing Li - One of the best experts on this subject based on the ideXlab platform.

  • ICME - Reducing memory bank conflict for embedded Multimedia Systems
    2004 IEEE International Conference on Multimedia and Expo (ICME) (IEEE Cat. No.04TH8763), 2004
    Co-Authors: Qi Zhang, Qing Li
    Abstract:

    Memory bank conflict is an important issue to be addressed to enhance the performance of embedded Multimedia Systems. This paper presents an analysis of the memory bank conflict problem. Based on the analysis, a novel scheme utilizing single instruction multiple data (SIMD) and array padding technique is introduced to reduce the memory bank conflict phenomenon. Since the array padding distance has a great impact on the overall conflict reduction, we propose a model-based confliction estimation scheme and a probabilistic model to determine the optimal padding distance. Experimental results are given to demonstrate the effectiveness of the proposed scheme

Francky Catthoor - One of the best experts on this subject based on the ideXlab platform.

  • Experience with Widening Based Equivalence Checking in Realistic Multimedia Systems
    Journal of Electronic Testing, 2010
    Co-Authors: Sven Verdoolaege, Martin Palkovic, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor
    Abstract:

    The application of loop and data transformations to array and loop intensive programs is crucial to obtain a good performance. Designers often apply these transformations manually or semi-automatically. For the class of static affine programs, automatic methods exist for proving the correctness of these transformations. Realistic Multimedia Systems, however, often contain constructs that fall outside of this class. We present an extension of a widening based approach to handle the most relevant of these constructs, viz. accesses to array slices, data dependent accesses and data dependent assignments, and report on some experiments with non-trivial applications.

  • experience with widening based equivalence checking in realistic Multimedia Systems
    High Level Design Validation and Test, 2009
    Co-Authors: Sven Verdoolaege, Martin Palkovic, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor
    Abstract:

    Designers often apply manual or semi-automatic loop and data transformations on array and loop intensive programs to improve performance. For the class of static affine programs, automatic methods exist for proving the correctness of these transformations. Realistic Multimedia Systems, however, often contain constructs that fall outside of this class. We present an extension of a widening based approach to handle the most relevant of these constructs, viz. accesses to array slices and data dependent accesses, and report on some experiments with non-trivial applications.