The Experts below are selected from a list of 8619 Experts worldwide ranked by ideXlab platform
Edwin H M Sha - One of the best experts on this subject based on the ideXlab platform.
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Algorithms and analysis of scheduling for loops with minimum switching
2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.
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Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering, 2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.Department of Computin
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loop scheduling for real time dsps with minimum switching activities on Multiple Functional Unit architectures
Embedded and Ubiquitous Computing, 2004Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Bin XiaoAbstract:This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on Multiple-Functional-Unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.
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EUC - Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures
Embedded and Ubiquitous Computing, 2004Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Bin XiaoAbstract:This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on Multiple-Functional-Unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.
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EUC - Optimizing address assignment for scheduling embedded DSPs
Embedded and Ubiquitous Computing, 2004Co-Authors: Chun Xue, Zili Shao, Edwin H M Sha, Bin XiaoAbstract:DSP architecture typically provides indirect addressing modes with auto-increment and auto-decrement. Subsuming the address arithmetic into auto-increment and auto-decrement modes improves the size and performance of generated code. A lot of previous work has been done on address assignment optimization to achieve code size reduction by minimizing address operations for single Functional Unit processors. However, minimizing address operations alone may not directly reduce code size and schedule length for Multiple-Functional-Unit processors. In this paper, we exploit address assignment and scheduling for Multiple Functional Units processors. Our approach is to first construct a nice address assignment and then do scheduling. By fully taking advantage of the address assignment during scheduling, code size and schedule length can be significantly reduced. We propose a Multiple-Functional-Unit algorithm to do both address assignment and scheduling. The experimental results show that our algorithm can greatly reduce code size and schedule length compared to the previous work.
Zili Shao - One of the best experts on this subject based on the ideXlab platform.
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Algorithms and analysis of scheduling for loops with minimum switching
2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.
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Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering, 2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.Department of Computin
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loop scheduling for real time dsps with minimum switching activities on Multiple Functional Unit architectures
Embedded and Ubiquitous Computing, 2004Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Bin XiaoAbstract:This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on Multiple-Functional-Unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.
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EUC - Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures
Embedded and Ubiquitous Computing, 2004Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Bin XiaoAbstract:This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on Multiple-Functional-Unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.
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EUC - Optimizing address assignment for scheduling embedded DSPs
Embedded and Ubiquitous Computing, 2004Co-Authors: Chun Xue, Zili Shao, Edwin H M Sha, Bin XiaoAbstract:DSP architecture typically provides indirect addressing modes with auto-increment and auto-decrement. Subsuming the address arithmetic into auto-increment and auto-decrement modes improves the size and performance of generated code. A lot of previous work has been done on address assignment optimization to achieve code size reduction by minimizing address operations for single Functional Unit processors. However, minimizing address operations alone may not directly reduce code size and schedule length for Multiple-Functional-Unit processors. In this paper, we exploit address assignment and scheduling for Multiple Functional Units processors. Our approach is to first construct a nice address assignment and then do scheduling. By fully taking advantage of the address assignment during scheduling, code size and schedule length can be significantly reduced. We propose a Multiple-Functional-Unit algorithm to do both address assignment and scheduling. The experimental results show that our algorithm can greatly reduce code size and schedule length compared to the previous work.
Bin Xiao - One of the best experts on this subject based on the ideXlab platform.
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Algorithms and analysis of scheduling for loops with minimum switching
2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.
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Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering, 2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.Department of Computin
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loop scheduling for real time dsps with minimum switching activities on Multiple Functional Unit architectures
Embedded and Ubiquitous Computing, 2004Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Bin XiaoAbstract:This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on Multiple-Functional-Unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.
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EUC - Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures
Embedded and Ubiquitous Computing, 2004Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Bin XiaoAbstract:This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on Multiple-Functional-Unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.
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EUC - Optimizing address assignment for scheduling embedded DSPs
Embedded and Ubiquitous Computing, 2004Co-Authors: Chun Xue, Zili Shao, Edwin H M Sha, Bin XiaoAbstract:DSP architecture typically provides indirect addressing modes with auto-increment and auto-decrement. Subsuming the address arithmetic into auto-increment and auto-decrement modes improves the size and performance of generated code. A lot of previous work has been done on address assignment optimization to achieve code size reduction by minimizing address operations for single Functional Unit processors. However, minimizing address operations alone may not directly reduce code size and schedule length for Multiple-Functional-Unit processors. In this paper, we exploit address assignment and scheduling for Multiple Functional Units processors. Our approach is to first construct a nice address assignment and then do scheduling. By fully taking advantage of the address assignment during scheduling, code size and schedule length can be significantly reduced. We propose a Multiple-Functional-Unit algorithm to do both address assignment and scheduling. The experimental results show that our algorithm can greatly reduce code size and schedule length compared to the previous work.
Chun Xue - One of the best experts on this subject based on the ideXlab platform.
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Algorithms and analysis of scheduling for loops with minimum switching
2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.
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Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering, 2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.Department of Computin
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EUC - Optimizing address assignment for scheduling embedded DSPs
Embedded and Ubiquitous Computing, 2004Co-Authors: Chun Xue, Zili Shao, Edwin H M Sha, Bin XiaoAbstract:DSP architecture typically provides indirect addressing modes with auto-increment and auto-decrement. Subsuming the address arithmetic into auto-increment and auto-decrement modes improves the size and performance of generated code. A lot of previous work has been done on address assignment optimization to achieve code size reduction by minimizing address operations for single Functional Unit processors. However, minimizing address operations alone may not directly reduce code size and schedule length for Multiple-Functional-Unit processors. In this paper, we exploit address assignment and scheduling for Multiple Functional Units processors. Our approach is to first construct a nice address assignment and then do scheduling. By fully taking advantage of the address assignment during scheduling, code size and schedule length can be significantly reduced. We propose a Multiple-Functional-Unit algorithm to do both address assignment and scheduling. The experimental results show that our algorithm can greatly reduce code size and schedule length compared to the previous work.
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ICASSP (5) - Optimizing DSP scheduling via address assignment with array and loop transformation
Proceedings. (ICASSP '05). IEEE International Conference on Acoustics Speech and Signal Processing 2005., 1Co-Authors: Chun Xue, Zili Shao, Ying Chen, Edwin H M ShaAbstract:Reducing address arithmetic instructions by optimization of address offset assignment greatly improves the performance of DSP applications. However, minimizing address operations alone may not directly reduce code size and schedule length for Multiple Functional Units DSPs. In this paper, we exploit address assignment and scheduling for application with loops on Multiple Functional Unit DSPs. Array transformation is used in our approach to leverage the indirect addressing modes provided by most of the DSP architectures. An algorithm, address instruction reduction loop scheduling (AIRLS), is proposed. The algorithm utilizes the techniques of rotation scheduling, address assignment and array transformation to minimize both address instructions and schedule length. Compared to the list scheduling, AIRLS shows an average reduction of 35.4% in schedule length and an average reduction of 38.3% in address instructions. Compared to the rotation scheduling, AIRLS shows an average reduction of 19.2% in schedule length and 39.5% in the number of address instructions.
Qingfeng Zhuge - One of the best experts on this subject based on the ideXlab platform.
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Algorithms and analysis of scheduling for loops with minimum switching
2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.
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Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering, 2006Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Chun Xue, Bin XiaoAbstract:Switching activity and schedule length are the two of the most important factors in power dissipation. This paper studies the scheduling problem that minimises both schedule length and switching activities for applications with loops on Multiple Functional Unit architectures. We show that, to find a schedule that has the minimal switching activities among all minimum latency schedules with or without resource constraints is NP-complete. Although the minimum latency scheduling problem is polynomial time solvable if there is no resource constraint or only one Functional Unit (FU), the problem becomes NP-complete when switching activities are considered as the second constraint. An algorithm, Power Reduction Rotation Scheduling (PRRS), is proposed. The algorithm attempts to minimise both switching activities and schedule length while performing scheduling and allocation simultaneously. Compared with the list scheduling, PRRS shows an average of 20.1% reduction in schedule length and 52.2% reduction in bus switching activities. Our algorithm also shows better performance than the approach that considers scheduling and allocation in separate phases.Department of Computin
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loop scheduling for real time dsps with minimum switching activities on Multiple Functional Unit architectures
Embedded and Ubiquitous Computing, 2004Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Bin XiaoAbstract:This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on Multiple-Functional-Unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.
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EUC - Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures
Embedded and Ubiquitous Computing, 2004Co-Authors: Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin H M Sha, Bin XiaoAbstract:This paper studies the scheduling problem that minimizes both schedule length and switching activities for applications with loops on Multiple-Functional-Unit architectures. We formally prove that to find a schedule that has the minimal switching activities among all minimum-latency schedules with or without resource constraints is NP-complete. An algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), is proposed to minimize both schedule length and switching activities. In SAMLS, the best schedule is selected from the ones generated from a given initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show our algorithm can greatly reduce both schedule length and switching activities compared with the previous work.
