The Experts below are selected from a list of 14580 Experts worldwide ranked by ideXlab platform
Manjusha Shankaradas - One of the best experts on this subject based on the ideXlab platform.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
International Solid-State Circuits Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, process, voltage, and temperature. The PLL achieves a Multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5 V.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
Design Automation Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, and PVT. The PLL achieves a Multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.
John George Maneatis - One of the best experts on this subject based on the ideXlab platform.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
International Solid-State Circuits Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, process, voltage, and temperature. The PLL achieves a Multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5 V.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
Design Automation Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, and PVT. The PLL achieves a Multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.
Jay Maxey - One of the best experts on this subject based on the ideXlab platform.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
International Solid-State Circuits Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, process, voltage, and temperature. The PLL achieves a Multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5 V.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
Design Automation Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, and PVT. The PLL achieves a Multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.
Iain Mcclatchie - One of the best experts on this subject based on the ideXlab platform.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
International Solid-State Circuits Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, process, voltage, and temperature. The PLL achieves a Multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5 V.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
Design Automation Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, and PVT. The PLL achieves a Multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.
Jaeha Kim - One of the best experts on this subject based on the ideXlab platform.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
International Solid-State Circuits Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, process, voltage, and temperature. The PLL achieves a Multiplication range of 1-4096 with less than 1.7% output jitter. Fabricated in 0.13-/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5 V.
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self biased high bandwidth low jitter 1 to 4096 multiplier clock generator pll
Design Automation Conference, 2003Co-Authors: John George Maneatis, Jaeha Kim, Iain Mcclatchie, Jay Maxey, Manjusha ShankaradasAbstract:A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of Multiplication Factor, output frequency, and PVT. The PLL achieves a Multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.
