The Experts below are selected from a list of 13338 Experts worldwide ranked by ideXlab platform
Hong-june Park - One of the best experts on this subject based on the ideXlab platform.
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a fir embedded phase interpolator based Noise Filtering for wide bandwidth fractional n pll
IEEE Journal of Solid-state Circuits, 2013Co-Authors: Hong-june ParkAbstract:This paper presents a 1-GHz ΔΣ fractional-N PLL with a Noise-Filtering scheme using a FIR-embedded phase interpolator. The proposed dual-referenced interpolation scheme compensates for systematic nonlinearity in circuit operation and increases immunity to mismatches in input seed phases. By multiple use of a dual-referenced interpolator, the phase interpolator realizes an embedded FIR Filtering for the quantization Noise from the ΔΣ modulator. The implemented PLL in 0.13- μm CMOS consumes 16.8 mW and shows a reduction of the phase Noise by 34 dB. With 3.2-MHz-wide bandwidth, the proposed Filtering technique achieves an in-band Noise of -106 dBc at 100 kHz and an out-of-band Noise of -107.5 dBc at 6 MHz.
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Phase-blender-based FIR Noise Filtering techniques for ΔΣ fractional-N PLL
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011Co-Authors: Hong-june ParkAbstract:This paper presents two FIR Noise Filtering techniques for ΔΣ fractional-N PLL, i.e. FIR-embedded PI and VCDL-based phase prediction. Without use of multiple CPs, PFDs and dividers, FIR-embedded PI realizes FIR Noise Filtering by averaging the output phases of interpolators. The FIR-embedded PI has been implemented in a 1 GHz ΔΣ fractional-N PLL and achieves the theoretically maximum bandwidth of 0.1×fref. The PLL, fabricated in a 0.13 μm CMOS, shows a reduction of phase Noise by 34 dB. The VCDL-based phase prediction scheme also successfully performs the effective FIR Filtering even without use of the multiple interpolators and provides a low power solution for FIR Noise Filtering in the design of ΔΣ fractional-N PLL.
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A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based Noise Filtering
2011 IEEE International Solid-State Circuits Conference, 2011Co-Authors: Hong-june ParkAbstract:This work presents a 1GHz ΔΣ fractional-N PLL based on the Noise Filtering by FIR-embedded phase interpolator (PI). The proposed PI scheme greatly improves phase linearity by a dual-referenced interpolation and realizes FIR Filtering without using multiple CPs, PFDs, and dividers. The designed fractional-N PLL shows a comparable phase-Noise performance to that of an integer-N PLL. The PLL is implemented in 0.13 μm CMOS technology.
Hong-fa Ho - One of the best experts on this subject based on the ideXlab platform.
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A Pipelined Architecture Design for Trilateral Noise Filtering
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Wen-chung Kao, Hong-shuo Tai, Chia-pin Shen, Jia-an Ye, Hong-fa HoAbstract:The trilateral Noise filter is capable of reducing both Gaussian and impulse image Noise. The filter combines domain filter, range filter, and rank-ordered absolute differences (ROAD) measurement into an integrated weighting function. The main issue of applying such a powerful Noise filter on real-time imaging systems is that its time complexity is extremely high. A possible way to remedying the problem is designing a dedicated hardware accelerator. In this paper, we propose a new pipelined architecture design for trilateral Noise Filtering. By using a bitwise operation for ROAD calculation and piecewise linear approximation for exponential function evaluation, the performance of these two time consuming operations are improved dramatically. The proposed architecture has been verified on a Xilinx FPGA board, and the system clock of this design can achieve 96.5 MHz which can process 4 MPixels/second.
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ISCAS - A Pipelined Architecture Design for Trilateral Noise Filtering
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Chia-pin Shen, Jia-an Ye, Hong-fa HoAbstract:The trilateral Noise filter is capable of reducing both Gaussian and impulse image Noise. The filter combines domain filter, range filter, and rank-ordered absolute differences (ROAD) measurement into an integrated weighting function. The main issue of applying such a powerful Noise filter on real-time imaging systems is that its time complexity is extremely high. A possible way to remedying the problem is designing a dedicated hardware accelerator. In this paper, we propose a new pipelined architecture design for trilateral Noise Filtering. By using a bitwise operation for ROAD calculation and piecewise linear approximation for exponential function evaluation, the performance of these two time consuming operations are improved dramatically. The proposed architecture has been verified on a Xilinx FPGA board, and the system clock of this design can achieve 96.5 MHz which can process 4 MPixels/second.
A. Beghdadi - One of the best experts on this subject based on the ideXlab platform.
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Noise Filtering using Empirical Mode Decomposition
2007 9th International Symposium on Signal Processing and Its Applications, 2007Co-Authors: A.o. Boudraa, J.c. Cexus, S. Benramdane, A. BeghdadiAbstract:In this paper a Noise Filtering method using the empirical mode decomposition (EMD) is proposed. The noisy signal is decomposed into oscillatory components called intrinsic mode functions (IMFs) using a process referred to as sifting. The basic idea of the proposed scheme is the partial re-construction of the signal using the IMFs corresponding to the most important structures of the signal (low frequency modes). A new criterion is proposed to determine the IMF after which the energy distribution of the important structures of the signal overcomes that of the Noise and that of the high frequency components of the signal. The method is tested on simulated and real signals.
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A Noise-Filtering method using a local information measure
IEEE Transactions on Image Processing, 1997Co-Authors: A. Beghdadi, A. KhellafAbstract:A nonlinear-Noise Filtering method for image processing, based on the entropy concept is developed and compared to the well-known median filter and to the center weighted median filter (CWM). The performance of the proposed method is evaluated through subjective and objective criteria. It is shown that this method performs better than the classical median for different types of Noise and can perform better than the CWM filter in some cases.
Thomas Sikora - One of the best experts on this subject based on the ideXlab platform.
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ICME - Noise Filtering method for color images based on LDA and nonlinear diffusion
2008 IEEE International Conference on Multimedia and Expo, 2008Co-Authors: Thomas SikoraAbstract:The purpose of Noise Filtering for images is to preserve features such as edge or corners in images, while reducing Noise. Recent Noise Filtering algorithms based on diffusion equation shows the satisfactory results to some extent, if the Noise is additive Gaussian Noise. However, if the Noise is not additive Gaussian Noise, the Filtering result is not satisfactory. In this paper, we propose a Noise Filtering method for color images based on LDA and nonlinear diffusion, which makes use of a common diffusion control. Experimental results with images degraded by additive Gaussian Noise, salt and pepper Noise, and multiplicative Noise are presented.
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Noise Filtering method for color images based on LDA and nonlinear diffusion
2008 IEEE International Conference on Multimedia and Expo, 2008Co-Authors: Thomas SikoraAbstract:The purpose of Noise Filtering for images is to preserve features such as edge or corners in images, while reducing Noise. Recent Noise Filtering algorithms based on diffusion equation shows the satisfactory results to some extent, if the Noise is additive Gaussian Noise. However, if the Noise is not additive Gaussian Noise, the Filtering result is not satisfactory. In this paper, we propose a Noise Filtering method for color images based on LDA and nonlinear diffusion, which makes use of a common diffusion control. Experimental results with images degraded by additive Gaussian Noise, salt and pepper Noise, and multiplicative Noise are presented.
Wen-chung Kao - One of the best experts on this subject based on the ideXlab platform.
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A Pipelined Architecture Design for Trilateral Noise Filtering
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Wen-chung Kao, Hong-shuo Tai, Chia-pin Shen, Jia-an Ye, Hong-fa HoAbstract:The trilateral Noise filter is capable of reducing both Gaussian and impulse image Noise. The filter combines domain filter, range filter, and rank-ordered absolute differences (ROAD) measurement into an integrated weighting function. The main issue of applying such a powerful Noise filter on real-time imaging systems is that its time complexity is extremely high. A possible way to remedying the problem is designing a dedicated hardware accelerator. In this paper, we propose a new pipelined architecture design for trilateral Noise Filtering. By using a bitwise operation for ROAD calculation and piecewise linear approximation for exponential function evaluation, the performance of these two time consuming operations are improved dramatically. The proposed architecture has been verified on a Xilinx FPGA board, and the system clock of this design can achieve 96.5 MHz which can process 4 MPixels/second.