The Experts below are selected from a list of 5130 Experts worldwide ranked by ideXlab platform

Hossein Pourghassem - One of the best experts on this subject based on the ideXlab platform.

  • real time seizure prediction using rls filtering and interpolated Histogram feature based on hybrid optimization algorithm of bayesian classifier and hunting search
    Computer Methods and Programs in Biomedicine, 2016
    Co-Authors: Morteza Behnam, Hossein Pourghassem
    Abstract:

    We propose a density-based real-time seizure prediction algorithm based on a trained offline seizure detection algorithm.A novel feature based on polynomial model of interpolated Normalized Histogram is proposed.The optimal features are selected using a hybrid optimization algorithm based on Bayesian classifier and Hunting search.Enhanced RLS filter estimates EEG signal sample-by-sample and filtering parameters are tuned by density-based signal tracking.We predict 6.64 seconds of future samples and the seizure signal, with accuracy rate of 86.56% and precision rate of 86.53%. Background and objectivesEpileptic seizure prediction using EEG signal analysis is an important application for drug therapy and pediatric patient monitoring. Time series estimation to obtain the future samples of EEG signal has vital role for detecting seizure attack. In this paper, a novel density-based real-time seizure prediction algorithm based on a trained offline seizure detection algorithm is proposed. MethodsIn the offline seizure detection procedure, after signal preprocessing, Histogram-based statistical features are extracted from signal probability distribution. By defining a deterministic polynomial model on the Normalized Histogram, a novel syntactic feature that is named Interpolated Histogram Feature (IHF) is proposed. Moreover, with this feature, Seizure Distribution Model (SDM) as a descriptor of the seizure and non-seizure signals is presented. By using a novel hybrid optimization algorithm based on Bayesian classifier and Hunting Search (HuS) algorithm, the optimal features are selected. To detect the seizure attacks in the online mode, a Multi-Layer Perceptron (MLP) classifier is trained with the optimal features in the offline procedure. For online prediction, the enhanced Recursive Least Square (RLS) filter is applied to estimate sample-by-sample of the EEG signal. Also, a density-based signal tracking scenario is introduced to update and tune the parameters of RLS filtering algorithm. ResultsOur prediction algorithm is evaluated on 104 hours of EEG signals recorded from 23 pediatric patients. Our online signal prediction algorithm provides the accuracy rate of 86.56% and precision rate of 86.53% simultaneously using the trained MLP classifier from the offline mode. The recall rate of seizure prediction is 97.27% and the false prediction rate of 0.00215 per hour is achieved as well. Ultimately, the future samples of EEG signal are estimated, and the time of seizure signal prediction is also converged to 6.64 seconds. ConclusionIn our proposed real-time algorithm, by implementing a density-based signal tracking scenario, the future samples of signal with suitable time is predicted and the seizure is detected based on the optimal features from the IHF and Histogram-based statistical features with acceptable performance.

Morteza Behnam - One of the best experts on this subject based on the ideXlab platform.

  • real time seizure prediction using rls filtering and interpolated Histogram feature based on hybrid optimization algorithm of bayesian classifier and hunting search
    Computer Methods and Programs in Biomedicine, 2016
    Co-Authors: Morteza Behnam, Hossein Pourghassem
    Abstract:

    We propose a density-based real-time seizure prediction algorithm based on a trained offline seizure detection algorithm.A novel feature based on polynomial model of interpolated Normalized Histogram is proposed.The optimal features are selected using a hybrid optimization algorithm based on Bayesian classifier and Hunting search.Enhanced RLS filter estimates EEG signal sample-by-sample and filtering parameters are tuned by density-based signal tracking.We predict 6.64 seconds of future samples and the seizure signal, with accuracy rate of 86.56% and precision rate of 86.53%. Background and objectivesEpileptic seizure prediction using EEG signal analysis is an important application for drug therapy and pediatric patient monitoring. Time series estimation to obtain the future samples of EEG signal has vital role for detecting seizure attack. In this paper, a novel density-based real-time seizure prediction algorithm based on a trained offline seizure detection algorithm is proposed. MethodsIn the offline seizure detection procedure, after signal preprocessing, Histogram-based statistical features are extracted from signal probability distribution. By defining a deterministic polynomial model on the Normalized Histogram, a novel syntactic feature that is named Interpolated Histogram Feature (IHF) is proposed. Moreover, with this feature, Seizure Distribution Model (SDM) as a descriptor of the seizure and non-seizure signals is presented. By using a novel hybrid optimization algorithm based on Bayesian classifier and Hunting Search (HuS) algorithm, the optimal features are selected. To detect the seizure attacks in the online mode, a Multi-Layer Perceptron (MLP) classifier is trained with the optimal features in the offline procedure. For online prediction, the enhanced Recursive Least Square (RLS) filter is applied to estimate sample-by-sample of the EEG signal. Also, a density-based signal tracking scenario is introduced to update and tune the parameters of RLS filtering algorithm. ResultsOur prediction algorithm is evaluated on 104 hours of EEG signals recorded from 23 pediatric patients. Our online signal prediction algorithm provides the accuracy rate of 86.56% and precision rate of 86.53% simultaneously using the trained MLP classifier from the offline mode. The recall rate of seizure prediction is 97.27% and the false prediction rate of 0.00215 per hour is achieved as well. Ultimately, the future samples of EEG signal are estimated, and the time of seizure signal prediction is also converged to 6.64 seconds. ConclusionIn our proposed real-time algorithm, by implementing a density-based signal tracking scenario, the future samples of signal with suitable time is predicted and the seizure is detected based on the optimal features from the IHF and Histogram-based statistical features with acceptable performance.

Linares Barranco Alejandro - One of the best experts on this subject based on the ideXlab platform.

  • Efficient DMA transfers management on embedded Linux PSoC for Deep-Learning gestures recognition: Using Dynamic Vision Sensor and NullHop one-layer CNN accelerator to play RoShamBo
    ACM Digital Library, 2019
    Co-Authors: Ríos Navarro, José Antonio, Tapiador Morales Ricardo, Jiménez Moreno Gabriel, Linares Barranco Alejandro
    Abstract:

    This demonstration shows a Dynamic Vision Sensor able to capture visual motion at a speed equivalent to a highspeed camera (20k fps). The collected visual information is presented as Normalized Histogram to a CNN accelerator hardware, called NullHop, that is able to process a pre-trained CNN to play Roshambo against a human. The CNN designed for this purpose consist of 5 convolutional layers and a fully connected layer. The latency for processing one Histogram is 8ms. NullHop is deployed on the FPGA fabric of a PSoC from Xilinx, the Zynq 7100, which is based on a dual-core ARM computer and a Kintex-7 with 444K logic cells, integrated in the same chip. ARM computer is running Linux and a specific C++ controller is running the whole demo. This controller runs at user space in order to extract the maximum throughput thanks to an efficient use of the AXIStream, based of DMA transfers. This short delay needed to process one visual Histogram, allows us to average several consecutive classification outputs. Therefore, it provides the best estimation of the symbol that the user presents to the visual sensor. This output is then mapped to present the winner symbol within the 60ms latency that the brain considers acceptable before thinking that there is a trick.Ministerio de Economía y Competitividad TEC2016-77785-

  • Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification
    'SAGE Publications', 2019
    Co-Authors: Linares Barranco Alejandro, Ríos Navarro, José Antonio, Tapiador Morales Ricardo, Delbruck Tobi
    Abstract:

    Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware accelerators have populated during the last years to improve CPU or GPU based solutions. This technology is commonly prototyped and tested over FPGAs before being considered for ASIC fabrication for mass production. The use of commercial typical cameras (30fps) limits the capabilities of these systems for high speed applications. The use of dynamic vision sensors (DVS) that emulate the behaviour of a biological retina is taking an incremental importance to improve this applications due to its nature, where the information is represented by a continuous stream of spikes and the frames to be processed by the CNN are constructed collecting a fixed number of these spikes (called events). The faster an object is, the more events are produced by DVS, so the higher is the equivalent frame rate. Therefore, these DVS utilization allows to compute a frame at the maximum speed a CNN accelerator can offer. In this paper we present a VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation (AER) DVS retina to obtain a Normalized Histogram to be used by a particular CNN accelerator, called NullHop. VHDL is used to describe the circuit, and HLS for computation blocks, which are used to perform the normalization of a frame needed for the CNN. Results outperform previous implementations of frames collection and normalization using ARM processors running at 800MHz on a Zynq7100 in both latency and power consumption. A measured 67% speedup factor is presented for a Roshambo CNN real-time experiment running at 160fps peak rate.Ministerio de Economía y Competitividad TEC2016-77785-

  • Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification
    2019
    Co-Authors: Linares Barranco Alejandro, Tapiador Morales Ricardo, Rios-navarro Antonio, Delbruck Tobi
    Abstract:

    Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware accelerators have populated during the last years to improve CPU or GPU based solutions. This technology is commonly prototyped and tested over FPGAs before being considered for ASIC fabrication for mass production. The use of commercial typical cameras (30fps) limits the capabilities of these systems for high speed applications. The use of dynamic vision sensors (DVS) that emulate the behavior of a biological retina is taking an incremental importance to improve this applications due to its nature, where the information is represented by a continuous stream of spikes and the frames to be processed by the CNN are constructed collecting a fixed number of these spikes (called events). The faster an object is, the more events are produced by DVS, so the higher is the equivalent frame rate. Therefore, these DVS utilization allows to compute a frame at the maximum speed a CNN accelerator can offer. In this paper we present a VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation (AER) DVS retina to obtain a Normalized Histogram to be used by a particular CNN accelerator, called NullHop. VHDL is used to describe the circuit, and HLS for computation blocks, which are used to perform the normalization of a frame needed for the CNN. Results outperform previous implementations of frames collection and normalization using ARM processors running at 800MHz on a Zynq7100 in both latency and power consumption. A measured 67% speedup factor is presented for a Roshambo CNN real-time experiment running at 160fps peak rate.Comment: 7 page

Delbruck Tobi - One of the best experts on this subject based on the ideXlab platform.

  • Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification
    'SAGE Publications', 2019
    Co-Authors: Linares Barranco Alejandro, Ríos Navarro, José Antonio, Tapiador Morales Ricardo, Delbruck Tobi
    Abstract:

    Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware accelerators have populated during the last years to improve CPU or GPU based solutions. This technology is commonly prototyped and tested over FPGAs before being considered for ASIC fabrication for mass production. The use of commercial typical cameras (30fps) limits the capabilities of these systems for high speed applications. The use of dynamic vision sensors (DVS) that emulate the behaviour of a biological retina is taking an incremental importance to improve this applications due to its nature, where the information is represented by a continuous stream of spikes and the frames to be processed by the CNN are constructed collecting a fixed number of these spikes (called events). The faster an object is, the more events are produced by DVS, so the higher is the equivalent frame rate. Therefore, these DVS utilization allows to compute a frame at the maximum speed a CNN accelerator can offer. In this paper we present a VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation (AER) DVS retina to obtain a Normalized Histogram to be used by a particular CNN accelerator, called NullHop. VHDL is used to describe the circuit, and HLS for computation blocks, which are used to perform the normalization of a frame needed for the CNN. Results outperform previous implementations of frames collection and normalization using ARM processors running at 800MHz on a Zynq7100 in both latency and power consumption. A measured 67% speedup factor is presented for a Roshambo CNN real-time experiment running at 160fps peak rate.Ministerio de Economía y Competitividad TEC2016-77785-

  • Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification
    2019
    Co-Authors: Linares Barranco Alejandro, Tapiador Morales Ricardo, Rios-navarro Antonio, Delbruck Tobi
    Abstract:

    Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware accelerators have populated during the last years to improve CPU or GPU based solutions. This technology is commonly prototyped and tested over FPGAs before being considered for ASIC fabrication for mass production. The use of commercial typical cameras (30fps) limits the capabilities of these systems for high speed applications. The use of dynamic vision sensors (DVS) that emulate the behavior of a biological retina is taking an incremental importance to improve this applications due to its nature, where the information is represented by a continuous stream of spikes and the frames to be processed by the CNN are constructed collecting a fixed number of these spikes (called events). The faster an object is, the more events are produced by DVS, so the higher is the equivalent frame rate. Therefore, these DVS utilization allows to compute a frame at the maximum speed a CNN accelerator can offer. In this paper we present a VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation (AER) DVS retina to obtain a Normalized Histogram to be used by a particular CNN accelerator, called NullHop. VHDL is used to describe the circuit, and HLS for computation blocks, which are used to perform the normalization of a frame needed for the CNN. Results outperform previous implementations of frames collection and normalization using ARM processors running at 800MHz on a Zynq7100 in both latency and power consumption. A measured 67% speedup factor is presented for a Roshambo CNN real-time experiment running at 160fps peak rate.Comment: 7 page

Tapiador Morales Ricardo - One of the best experts on this subject based on the ideXlab platform.

  • Efficient DMA transfers management on embedded Linux PSoC for Deep-Learning gestures recognition: Using Dynamic Vision Sensor and NullHop one-layer CNN accelerator to play RoShamBo
    ACM Digital Library, 2019
    Co-Authors: Ríos Navarro, José Antonio, Tapiador Morales Ricardo, Jiménez Moreno Gabriel, Linares Barranco Alejandro
    Abstract:

    This demonstration shows a Dynamic Vision Sensor able to capture visual motion at a speed equivalent to a highspeed camera (20k fps). The collected visual information is presented as Normalized Histogram to a CNN accelerator hardware, called NullHop, that is able to process a pre-trained CNN to play Roshambo against a human. The CNN designed for this purpose consist of 5 convolutional layers and a fully connected layer. The latency for processing one Histogram is 8ms. NullHop is deployed on the FPGA fabric of a PSoC from Xilinx, the Zynq 7100, which is based on a dual-core ARM computer and a Kintex-7 with 444K logic cells, integrated in the same chip. ARM computer is running Linux and a specific C++ controller is running the whole demo. This controller runs at user space in order to extract the maximum throughput thanks to an efficient use of the AXIStream, based of DMA transfers. This short delay needed to process one visual Histogram, allows us to average several consecutive classification outputs. Therefore, it provides the best estimation of the symbol that the user presents to the visual sensor. This output is then mapped to present the winner symbol within the 60ms latency that the brain considers acceptable before thinking that there is a trick.Ministerio de Economía y Competitividad TEC2016-77785-

  • Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification
    'SAGE Publications', 2019
    Co-Authors: Linares Barranco Alejandro, Ríos Navarro, José Antonio, Tapiador Morales Ricardo, Delbruck Tobi
    Abstract:

    Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware accelerators have populated during the last years to improve CPU or GPU based solutions. This technology is commonly prototyped and tested over FPGAs before being considered for ASIC fabrication for mass production. The use of commercial typical cameras (30fps) limits the capabilities of these systems for high speed applications. The use of dynamic vision sensors (DVS) that emulate the behaviour of a biological retina is taking an incremental importance to improve this applications due to its nature, where the information is represented by a continuous stream of spikes and the frames to be processed by the CNN are constructed collecting a fixed number of these spikes (called events). The faster an object is, the more events are produced by DVS, so the higher is the equivalent frame rate. Therefore, these DVS utilization allows to compute a frame at the maximum speed a CNN accelerator can offer. In this paper we present a VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation (AER) DVS retina to obtain a Normalized Histogram to be used by a particular CNN accelerator, called NullHop. VHDL is used to describe the circuit, and HLS for computation blocks, which are used to perform the normalization of a frame needed for the CNN. Results outperform previous implementations of frames collection and normalization using ARM processors running at 800MHz on a Zynq7100 in both latency and power consumption. A measured 67% speedup factor is presented for a Roshambo CNN real-time experiment running at 160fps peak rate.Ministerio de Economía y Competitividad TEC2016-77785-

  • Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification
    2019
    Co-Authors: Linares Barranco Alejandro, Tapiador Morales Ricardo, Rios-navarro Antonio, Delbruck Tobi
    Abstract:

    Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware accelerators have populated during the last years to improve CPU or GPU based solutions. This technology is commonly prototyped and tested over FPGAs before being considered for ASIC fabrication for mass production. The use of commercial typical cameras (30fps) limits the capabilities of these systems for high speed applications. The use of dynamic vision sensors (DVS) that emulate the behavior of a biological retina is taking an incremental importance to improve this applications due to its nature, where the information is represented by a continuous stream of spikes and the frames to be processed by the CNN are constructed collecting a fixed number of these spikes (called events). The faster an object is, the more events are produced by DVS, so the higher is the equivalent frame rate. Therefore, these DVS utilization allows to compute a frame at the maximum speed a CNN accelerator can offer. In this paper we present a VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation (AER) DVS retina to obtain a Normalized Histogram to be used by a particular CNN accelerator, called NullHop. VHDL is used to describe the circuit, and HLS for computation blocks, which are used to perform the normalization of a frame needed for the CNN. Results outperform previous implementations of frames collection and normalization using ARM processors running at 800MHz on a Zynq7100 in both latency and power consumption. A measured 67% speedup factor is presented for a Roshambo CNN real-time experiment running at 160fps peak rate.Comment: 7 page