The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Yorito Sakano - One of the best experts on this subject based on the ideXlab platform.
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8 3 m pixel 480 fps global shutter cmos Image sensor with gain adaptive column adcs and chip on chip stacked integration
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Yusuke Oike, Kentaro Akiyama, Luong D Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito SakanoAbstract:This paper presents a 4K2K 480-fps global-shutter CMOS Image sensor with a super 35-mm format for a highly realistic digital video system. The sensor employs newly developed gain-adaptive column analog-to-digital converters to obtain input-referred dark random noise of 140 $\mu \text{V}_{\mathrm {rms}}$ for an input-referred full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintained the nonlinearity of the Output Image within 0.18%. A chip-on-chip integration process realized a front-illuminated Image sensor stacked with two diced logic chips through 38-K microbump interconnections. The global-shutter pixel achieved a parasitic light sensitivity of −99.6 dB. The 16-channel Output interfaces with 4.752 Gbps/ch were implemented in the stacked logic chips.
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an 8 3m pixel 480fps global shutter cmos Image sensor with gain adaptive column adcs and 2 on 1 stacked device structure
Symposium on VLSI Circuits, 2016Co-Authors: Yusuke Oike, Kentaro Akiyama, Luong D Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito SakanoAbstract:A 4K2K 480 fps global-shutter CMOS Image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 µV rms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of Output Image within 0.18 %. The 16-channel Output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.
Yusuke Oike - One of the best experts on this subject based on the ideXlab platform.
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8 3 m pixel 480 fps global shutter cmos Image sensor with gain adaptive column adcs and chip on chip stacked integration
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Yusuke Oike, Kentaro Akiyama, Luong D Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito SakanoAbstract:This paper presents a 4K2K 480-fps global-shutter CMOS Image sensor with a super 35-mm format for a highly realistic digital video system. The sensor employs newly developed gain-adaptive column analog-to-digital converters to obtain input-referred dark random noise of 140 $\mu \text{V}_{\mathrm {rms}}$ for an input-referred full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintained the nonlinearity of the Output Image within 0.18%. A chip-on-chip integration process realized a front-illuminated Image sensor stacked with two diced logic chips through 38-K microbump interconnections. The global-shutter pixel achieved a parasitic light sensitivity of −99.6 dB. The 16-channel Output interfaces with 4.752 Gbps/ch were implemented in the stacked logic chips.
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an 8 3m pixel 480fps global shutter cmos Image sensor with gain adaptive column adcs and 2 on 1 stacked device structure
Symposium on VLSI Circuits, 2016Co-Authors: Yusuke Oike, Kentaro Akiyama, Luong D Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito SakanoAbstract:A 4K2K 480 fps global-shutter CMOS Image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 µV rms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of Output Image within 0.18 %. The 16-channel Output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.
Robert Henderson - One of the best experts on this subject based on the ideXlab platform.
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320 240 oversampled digital single photon counting Image sensor
Symposium on VLSI Circuits, 2014Co-Authors: Neale Dutton, Luca Parmesan, Andrew J Holmes, Lindsay A Grant, Robert HendersonAbstract:A 320×240 single photon avalanche diode (SPAD) based single photon counting Image sensor is implemented in 0.13μm imaging CMOS with state of the art 8μm pixel pitch at 26.8% fill factor. The Imager is demonstrated operating as a global shutter (GS) oversampled binary Image sensor reading out at 5.14kFPS. Frames are accumulated in real time on FPGA to construct a 256 photon/8bit Output Image at 20FPS.
Akihiko Kato - One of the best experts on this subject based on the ideXlab platform.
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8 3 m pixel 480 fps global shutter cmos Image sensor with gain adaptive column adcs and chip on chip stacked integration
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Yusuke Oike, Kentaro Akiyama, Luong D Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito SakanoAbstract:This paper presents a 4K2K 480-fps global-shutter CMOS Image sensor with a super 35-mm format for a highly realistic digital video system. The sensor employs newly developed gain-adaptive column analog-to-digital converters to obtain input-referred dark random noise of 140 $\mu \text{V}_{\mathrm {rms}}$ for an input-referred full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintained the nonlinearity of the Output Image within 0.18%. A chip-on-chip integration process realized a front-illuminated Image sensor stacked with two diced logic chips through 38-K microbump interconnections. The global-shutter pixel achieved a parasitic light sensitivity of −99.6 dB. The 16-channel Output interfaces with 4.752 Gbps/ch were implemented in the stacked logic chips.
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an 8 3m pixel 480fps global shutter cmos Image sensor with gain adaptive column adcs and 2 on 1 stacked device structure
Symposium on VLSI Circuits, 2016Co-Authors: Yusuke Oike, Kentaro Akiyama, Luong D Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito SakanoAbstract:A 4K2K 480 fps global-shutter CMOS Image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 µV rms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of Output Image within 0.18 %. The 16-channel Output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.
Hiroshi Shiroshita - One of the best experts on this subject based on the ideXlab platform.
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8 3 m pixel 480 fps global shutter cmos Image sensor with gain adaptive column adcs and chip on chip stacked integration
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Yusuke Oike, Kentaro Akiyama, Luong D Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito SakanoAbstract:This paper presents a 4K2K 480-fps global-shutter CMOS Image sensor with a super 35-mm format for a highly realistic digital video system. The sensor employs newly developed gain-adaptive column analog-to-digital converters to obtain input-referred dark random noise of 140 $\mu \text{V}_{\mathrm {rms}}$ for an input-referred full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintained the nonlinearity of the Output Image within 0.18%. A chip-on-chip integration process realized a front-illuminated Image sensor stacked with two diced logic chips through 38-K microbump interconnections. The global-shutter pixel achieved a parasitic light sensitivity of −99.6 dB. The 16-channel Output interfaces with 4.752 Gbps/ch were implemented in the stacked logic chips.
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an 8 3m pixel 480fps global shutter cmos Image sensor with gain adaptive column adcs and 2 on 1 stacked device structure
Symposium on VLSI Circuits, 2016Co-Authors: Yusuke Oike, Kentaro Akiyama, Luong D Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito SakanoAbstract:A 4K2K 480 fps global-shutter CMOS Image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 µV rms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of Output Image within 0.18 %. The 16-channel Output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.