The Experts below are selected from a list of 321 Experts worldwide ranked by ideXlab platform
Taro Toyoizumi - One of the best experts on this subject based on the ideXlab platform.
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Learning poly-synaptic paths with traveling waves.
arXiv: Neurons and Cognition, 2021Co-Authors: Yoshiki Ito, Taro ToyoizumiAbstract:Traveling waves are commonly observed across the brain. While previous studies have suggested the role of traveling waves in learning, the mechanism is still unclear. We adopted a computational approach to investigate the effect of traveling waves on synaptic plasticity. Our results indicate that traveling waves facilitate the learning of poly-synaptic network-paths when combined with a reward-dependent local synaptic plasticity rule. We also demonstrate that traveling waves expedite finding the shortest paths and learning nonlinear input/Output-Mapping, such as exclusive or (XOR) function.
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Learning poly-synaptic paths with traveling waves.
PLoS computational biology, 2021Co-Authors: Yoshiki Ito, Taro ToyoizumiAbstract:Traveling waves are commonly observed across the brain. While previous studies have suggested the role of traveling waves in learning, the mechanism remains unclear. We adopted a computational approach to investigate the effect of traveling waves on synaptic plasticity. Our results indicate that traveling waves facilitate the learning of poly-synaptic network paths when combined with a reward-dependent local synaptic plasticity rule. We also demonstrate that traveling waves expedite finding the shortest paths and learning nonlinear input/Output Mapping, such as exclusive or (XOR) function.
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Learning distant paths with traveling waves
arXiv: Neurons and Cognition, 2019Co-Authors: Yoshiki Ito, Taro ToyoizumiAbstract:Traveling waves are commonly observed across the brain. While previous studies have suggested the role of traveling waves in learning, the mechanism is still unclear. We adopted a computational approach to investigate the effect of traveling waves on synaptic plasticity. Our results indicate that traveling waves facilitate learning of distant and indirectly connected network-paths when combined with a reward-based local synaptic plasticity rule. We demonstrate that traveling waves expedite finding the shortest paths and learning nonlinear input/Output-Mapping, such as the XOR function.
Sujit Dey - One of the best experts on this subject based on the ideXlab platform.
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a scalable software based self test methodology for programmable processors
Design Automation Conference, 2003Co-Authors: Li Chen, S Ravi, Anand Raghunathan, Sujit DeyAbstract:Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic scalable methodology for SBST that automates several key steps. The proposed methodology consists of (i) identifying test program templates that are well suited for test delivery to each module within the processor, (ii) extracting input/Output Mapping functions that capture the controllability/observability constraints imposed by a test program template for a specific module-under-test, (iii) generating module-level tests by representing the input/Output Mapping functions as virtual constraint circuits, and (iv) automatic synthesis of a software self-test program from the module-level tests. We propose novel RTL simulation-based techniques for template ranking and selection, and techniques based on the theory of statistical regression for extraction of input/Output Mapping functions. An important advantage of the proposed techniques is their scalability, which is necessitated by the significant and growing complexity of embedded processors.To demonstrate the utility of the proposed methodology, we have applied it to a commercial state-of-the-art embedded processor (Xtensa™ from Tensilica Inc.). We believe this is the first practical demonstration of software-based self-test on a processor of such complexity. Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.
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DAC - A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th conference on Design automation - DAC '03, 2003Co-Authors: Li Chen, S Ravi, Anand Raghunathan, Sujit DeyAbstract:Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic scalable methodology for SBST that automates several key steps. The proposed methodology consists of (i) identifying test program templates that are well suited for test delivery to each module within the processor, (ii) extracting input/Output Mapping functions that capture the controllability/observability constraints imposed by a test program template for a specific module-under-test, (iii) generating module-level tests by representing the input/Output Mapping functions as virtual constraint circuits, and (iv) automatic synthesis of a software self-test program from the module-level tests. We propose novel RTL simulation-based techniques for template ranking and selection, and techniques based on the theory of statistical regression for extraction of input/Output Mapping functions. An important advantage of the proposed techniques is their scalability, which is necessitated by the significant and growing complexity of embedded processors.To demonstrate the utility of the proposed methodology, we have applied it to a commercial state-of-the-art embedded processor (Xtensa™ from Tensilica Inc.). We believe this is the first practical demonstration of software-based self-test on a processor of such complexity. Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.
Yoshiki Ito - One of the best experts on this subject based on the ideXlab platform.
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Learning poly-synaptic paths with traveling waves.
arXiv: Neurons and Cognition, 2021Co-Authors: Yoshiki Ito, Taro ToyoizumiAbstract:Traveling waves are commonly observed across the brain. While previous studies have suggested the role of traveling waves in learning, the mechanism is still unclear. We adopted a computational approach to investigate the effect of traveling waves on synaptic plasticity. Our results indicate that traveling waves facilitate the learning of poly-synaptic network-paths when combined with a reward-dependent local synaptic plasticity rule. We also demonstrate that traveling waves expedite finding the shortest paths and learning nonlinear input/Output-Mapping, such as exclusive or (XOR) function.
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Learning poly-synaptic paths with traveling waves.
PLoS computational biology, 2021Co-Authors: Yoshiki Ito, Taro ToyoizumiAbstract:Traveling waves are commonly observed across the brain. While previous studies have suggested the role of traveling waves in learning, the mechanism remains unclear. We adopted a computational approach to investigate the effect of traveling waves on synaptic plasticity. Our results indicate that traveling waves facilitate the learning of poly-synaptic network paths when combined with a reward-dependent local synaptic plasticity rule. We also demonstrate that traveling waves expedite finding the shortest paths and learning nonlinear input/Output Mapping, such as exclusive or (XOR) function.
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Learning distant paths with traveling waves
arXiv: Neurons and Cognition, 2019Co-Authors: Yoshiki Ito, Taro ToyoizumiAbstract:Traveling waves are commonly observed across the brain. While previous studies have suggested the role of traveling waves in learning, the mechanism is still unclear. We adopted a computational approach to investigate the effect of traveling waves on synaptic plasticity. Our results indicate that traveling waves facilitate learning of distant and indirectly connected network-paths when combined with a reward-based local synaptic plasticity rule. We demonstrate that traveling waves expedite finding the shortest paths and learning nonlinear input/Output-Mapping, such as the XOR function.
Chanwoong Jung - One of the best experts on this subject based on the ideXlab platform.
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laser spot detection based computer interface system using autoassociative multilayer perceptron with input to Output Mapping sensitive error back propagation learning algorithm
Optical Engineering, 2011Co-Authors: Sungmoon Jeong, Chanwoong Jung, Jae Hoon ShimAbstract:This paper presents a new computer interface system based on laser spot detection and moving pattern analysis of the detected laser spots in real-time processing. We propose a systematic method that uses either the frame difference of successive input images or an autoassociative multilayer perceptron (AAMLP) to detect laser spots. The AAMLP is applied only to areas of the input images where the frame difference of the successive images is not effective for detecting laser spots. In order to enhance the detection performance, the AAMLP is trained by a new training algorithm that increases the sensitivity of the input-to-Output Mapping of the AAMLP allowing a small variation in the input feature of the laser spot image to be successfully indicated. The proposed interface system is also able to keep track of the laser spot and recognize gesture commands. The moving pattern of the laser spot is recognized by using a multilayer perception. It is experimentally shown that the proposed computer interface system is fast enough for real-time operation with reliable accuracy.
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Novel input and Output Mapping-sensitive error back propagation learning algorithm for detecting small input feature variations
Neural Computing and Applications, 2011Co-Authors: Chanwoong Jung, Cheol-su Kim, Sang-woo Ban, Il-kyu Hwang, Minho LeeAbstract:This paper proposes a new error back propagation learning algorithm that properly enhances the sensitivity of input and Output Mapping by applying a high-pass filter characteristic to the conventional error back propagation learning algorithm, allowing small input feature variations to be successfully indicated. For the sensitive discrimination of novel class data with slightly different characteristics from the normal class data, the cost function in the proposed neural network algorithm is modified by further increasing the input and Output sensitivity, where weight update rules are used to minimize the cost function using a gradient descent method. The proposed algorithm is applied to an auto-associative multilayer perceptron neural network and its performance evaluated with two real-world applications: a laser spot detection-based computer interface system for detecting a laser spot in complex backgrounds and an automatic inspection system for the reliable detection of Mura defects that occur during the manufacture of flat panel liquid crystal displays. When compared with the conventional error back propagation learning algorithm, the proposed algorithm shows a better performance as regards detecting small input feature variations by increasing the input–Output Mapping sensitivity.
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Laser spot pattern recognition based computer interface using I/O Mapping sensitive neural networks
2011 IEEE International Conference on Consumer Electronics (ICCE), 2011Co-Authors: Chanwoong JungAbstract:This paper presents a new computer interface system based on laser points pattern recognition in beam projection, which can generate five interfacing commands. A new input and Output Mapping sensitive error back propagation (SBEP) algorithm for a multilayer neural network is proposed for successfully localizing laser spots in beam projection.
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ICONIP (2) - Input and Output Mapping sensitive auto-associative multilayer perceptron for computer interface system based on image processing of laser pointer spot
Lecture Notes in Computer Science, 2010Co-Authors: Chanwoong Jung, Sang-woo Ban, Sungmoon Jeong, Minho LeeAbstract:In this paper, we propose a new auto-associative multilayer perceptron (AAMLP) that properly enhances the sensitivity of input and Output (I/O) Mapping by applying a high pass filter characteristic to the conventional error back propagation learning algorithm, through which small variation of input feature is successfully indicated. The proposed model aims to sensitively discriminate a data of one cluster with small different characteristics against another different cluster's data. Objective function for the proposed neural network is modified by additionally considering an input and Output sensitivity, in which the weight update rules are induced in the manner of minimizing the objective function by a gradient descent method. The proposed model is applied for a real application system to localize laser spots in a beam projected image, which can be utilized as a new computer interface system for dynamic interaction with audiences in presentation or meeting environment. Complexity of laser spot localization is very wide, therefore it is very simple in some cases, but it becomes very tough when the laser spot area has very slightly different characteristic compared with the corresponding area in a beam projected image. The proposed neural network model shows better performance by increasing the input-Output Mapping sensitivity than the conventional AAMLP.
Li Chen - One of the best experts on this subject based on the ideXlab platform.
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a scalable software based self test methodology for programmable processors
Design Automation Conference, 2003Co-Authors: Li Chen, S Ravi, Anand Raghunathan, Sujit DeyAbstract:Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic scalable methodology for SBST that automates several key steps. The proposed methodology consists of (i) identifying test program templates that are well suited for test delivery to each module within the processor, (ii) extracting input/Output Mapping functions that capture the controllability/observability constraints imposed by a test program template for a specific module-under-test, (iii) generating module-level tests by representing the input/Output Mapping functions as virtual constraint circuits, and (iv) automatic synthesis of a software self-test program from the module-level tests. We propose novel RTL simulation-based techniques for template ranking and selection, and techniques based on the theory of statistical regression for extraction of input/Output Mapping functions. An important advantage of the proposed techniques is their scalability, which is necessitated by the significant and growing complexity of embedded processors.To demonstrate the utility of the proposed methodology, we have applied it to a commercial state-of-the-art embedded processor (Xtensa™ from Tensilica Inc.). We believe this is the first practical demonstration of software-based self-test on a processor of such complexity. Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.
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DAC - A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th conference on Design automation - DAC '03, 2003Co-Authors: Li Chen, S Ravi, Anand Raghunathan, Sujit DeyAbstract:Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) that contain them. While early work on SBST has proposed several promising ideas, many challenges remain in applying SBST to realistic embedded processors. We propose a systematic scalable methodology for SBST that automates several key steps. The proposed methodology consists of (i) identifying test program templates that are well suited for test delivery to each module within the processor, (ii) extracting input/Output Mapping functions that capture the controllability/observability constraints imposed by a test program template for a specific module-under-test, (iii) generating module-level tests by representing the input/Output Mapping functions as virtual constraint circuits, and (iv) automatic synthesis of a software self-test program from the module-level tests. We propose novel RTL simulation-based techniques for template ranking and selection, and techniques based on the theory of statistical regression for extraction of input/Output Mapping functions. An important advantage of the proposed techniques is their scalability, which is necessitated by the significant and growing complexity of embedded processors.To demonstrate the utility of the proposed methodology, we have applied it to a commercial state-of-the-art embedded processor (Xtensa™ from Tensilica Inc.). We believe this is the first practical demonstration of software-based self-test on a processor of such complexity. Experimental results demonstrate that software self-test programs generated using the proposed methodology are able to detect most (95.2%) of the functionally testable faults, and achieve significant simultaneous improvements in fault coverage and test length compared with conventional functional test.