The Experts below are selected from a list of 87 Experts worldwide ranked by ideXlab platform
Qinglong Han - One of the best experts on this subject based on the ideXlab platform.
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event triggered dissipative control for networked stochastic systems under non uniform sampling
Information Sciences, 2018Co-Authors: Jia Wang, Xianming Zhang, Yufeng Lin, Qinglong HanAbstract:Abstract This paper is concerned with dissipative control for networked stochastic systems with an event-triggered transmission mechanism. Different from some existing results, signals from a physical plant are sampled non-uniformly . In order to save precious communication resources, a data-Packet Processor is introduced to choose necessary data-Packets based on a flexible event-triggered condition. By establishing an integral inequality in stochastic setting, which is regarded as a counterpart of Wirtinger-based inequality, a criterion is derived such that the resultant closed-loop system is mean-square stable and dissipative. This criterion is then used to calculate suitable event-triggered controllers in terms of solutions to linear matrix inequalities. An air vehicle system is finally taken to substantiate the validity of the proposed method.
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a decentralized event triggered dissipative control scheme for systems with multiple sensors to sample the system outputs
IEEE Transactions on Systems Man and Cybernetics, 2016Co-Authors: Xianming Zhang, Qinglong HanAbstract:This paper is concerned with decentralized event-triggered dissipative control for systems with the entries of the system outputs having different physical properties. Depending on these different physical properties, the entries of the system outputs are grouped into multiple nodes. A number of sensors are used to sample the signals from different nodes. A decentralized event-triggering scheme is introduced to select those necessary sampled-data Packets to be transmitted so that communication resources can be saved significantly while preserving the prescribed closed-loop performance. First, in order to organize the decentralized data Packets transmitted from the sensor nodes, a data Packet Processor (DPP) is used to generate a new signal to be held by the zero-order-hold once the signal stored by the DPP is updated at some time instant. Second, under the mechanism of the DPP, the resulting closed-loop system is modeled as a linear system with an interval time-varying delay. A sufficient condition is derived such that the closed-loop system is asymptotically stable and strictly $ {(Q_{0},S_{0},R_{0})}$ -dissipative, where $ {Q_{0},S_{0}}$ , and $ {R_{0}}$ are real matrices of appropriate dimensions with $ {Q_{0}}$ and $ {R_{0}}$ symmetric. Third, suitable output-based controllers can be designed based on solutions to a set of a linear matrix inequality. Finally, two examples are given to demonstrate the effectiveness of the proposed method.
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event based h filtering for sampled data systems
Automatica, 2015Co-Authors: Xianming Zhang, Qinglong HanAbstract:This paper is concerned with event-based H ∞ filtering for sampled-data systems. First, an event-based data Packet Processor is introduced to release sampled measurement outputs only if an event condition is violated. As a result, communication resources can be saved significantly while preserving the desired H ∞ performance. Second, the resulting filtering error system is modeled as a system with an interval time-varying delay. By employing the Lyapunov-Krasovskii functional approach, a new bounded real lemma (BRL) is established such that the filtering error system is asymptotically stable with the prescribed H ∞ performance. Third, by performing an invertible linear transformation on the filtering error system, a linear matrix inequality (LMI)-based sufficient condition, which is equivalent to the condition in the BRL, is obtained on the feasibility of the event-based H ∞ filtering problem. Consequently, suitable H ∞ filters and the event parameters in the event condition can be co-designed provided that a set of LMIs are satisfied. Finally, a mechanical system with two masses and two springs is given to show the effectiveness of the proposed method.
Dario Rossi - One of the best experts on this subject based on the ideXlab platform.
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high speed data plane and network functions virtualization by vectorizing Packet processing
Computer Networks, 2019Co-Authors: Leonardo Linguaglossa, Salvatore Pontarelli, David Richard Barach, Dario Rossi, Damjan Marjon, Pierre PfisterAbstract:Abstract In the last decade, a number of frameworks started to appear that implement, directly in user-space with kernel-bypass mode, high-speed software data plane functionalities on commodity hardware. This may be the key to replace specific hardware-based middleboxes with custom pieces of software, as advocated by the recent Network Function Virtualization (NFV) paradigm. Vector Packet Processor (VPP) is one of such frameworks, representing an interesting point in the design space in that it offers: (i) in user-space networking, (ii) the flexibility of a modular router (Click and variants) with (iii) high-speed performance (several millions of Packets per second on a single CPU core), achieved through techniques such as batch processing that have become commonplace in high-speed networking stacks (e.g. netmap or DPDK). Similarly to Click, VPP lets users arrange functions as a processing graph, providing a full-blown stack of network functions. However, unlike Click where the whole tree is traversed for each Packet, in VPP each traversed node processes all Packets in the batch (or vector) before moving to the next node. This design choice enables several code optimizations that greatly improve the achievable throughput. This paper introduces the main VPP concepts and architecture, and experimentally evaluates the impact of its design choices (such as batch Packet processing) on its performance.
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TupleMerge: Fast Software Packet Processing for Online Packet Classification
IEEE ACM Transactions on Networking, 2019Co-Authors: James Daly, Salvatore Pontarelli, Leonardo Linguaglossa, Dario Rossi, Valerio Bruschi, Jerome Tollet, Eric Torng, Andrew YourtchenkoAbstract:Packet classification is an important part of many networking devices, such as routers and firewalls. Software-defined networking (SDN) heavily relies on online Packet classification which must efficiently process two different streams: incoming Packets to classify and rules to update. This rules out many offline Packet classification algorithms that do not support fast updates. We propose a novel online classification algorithm, TupleMerge (TM), derived from tuple space search (TSS), the Packet classifier used by Open vSwitch (OVS). TM improves upon TSS by combining hash tables which contain rules with similar characteristics. This greatly reduces classification time preserving similar performance in updates. We validate the effectiveness of TM using both simulation and deployment in a full-fledged software router, specifically within the vector Packet Processor (VPP). In our simulation results, which focus solely on the efficiency of the classification algorithm, we demonstrate that TM outperforms all other state of the art methods, including TSS, PartitionSort (PS), and SAX-PAC. For example, TM is 34% faster at classifying Packets and 30% faster at updating rules than PS. We then experimentally evaluate TM deployed within the VPP framework comparing TM against linear search and TSS, and also against TSS within the OVS framework. This validation of deployed implementations is important as SDN frameworks have several optimizations such as caches that may minimize the influence of a classification algorithm. Our experimental results clearly validate the effectiveness of TM. VPP TM classifies Packets nearly two orders of magnitude faster than VPP TSS and at least one order of magnitude faster than OVS TSS.
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high speed software data plane via vectorized Packet processing
IEEE Communications Magazine, 2018Co-Authors: David Richard Barach, Salvatore Pontarelli, Leonardo Linguaglossa, Damjan Marion, Pierre Pfister, Dario RossiAbstract:In the last decade, a number of frameworks started to appear that implement, directly in userspace with kernel-bypass mode, high-speed software data plane functionalities on commodity hardware. Vector Packet Processor (VPP) is one of such frameworks, representing an interesting point in the design space in that it offers, in userspace networking, the flexibility of a modular router (Click and variants), with the benefits provided by techniques such as batch processing that have become commonplace in high-speed networking stacks (such as netmap or DPDK). Similarly to Click, VPP lets users arrange functions as a processing graph, providing a full-blown stack of network functions. However, unlike Click, where the whole tree is traversed for each Packet, in VPP each traversed node processes all Packets in the batch (called vector) before moving to the next node. This design choice enables several code optimizations that greatly improve the achievable processing throughput. This article introduces the main VPP concepts and architecture, and experimentally evaluates the impact of design choices (such as batch Packet processing) on performance.
Simon Kunzli - One of the best experts on this subject based on the ideXlab platform.
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chapter 4 design space exploration of network Processor architectures
Network Processor Design, 2003Co-Authors: Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon KunzliAbstract:It is noted that network Processors (NPs) generally consist of multiple processing units such as CPU cores, microengines, and dedicated hardware for computing-intensive tasks, memory units, caches, interconnections, and I/O interfaces. Following a system-on-a-chip (SoC) design method, these resources are then put on a single chip and they must interoperate in order to perform Packet processing tasks at line speed. The process of determining the optimal hardware and software architecture for such Processors includes issues involving resource allocation and partitioning. The chapter presents a framework for the design space exploration of embedded systems. It is observed that the architecture exploration and evaluation of network Processors involve many tradeoffs and a complex interplay between hardware and software. The chapter focuses on high level of abstraction, where the goal is to quickly identify interesting architectures that can be further evaluated by taking lower-level details into account. Task models, task scheduling, operating system issues, and Packet Processor architectures collectively play a role in different phases of the design space exploration of Packet Processor devices.
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a framework for evaluating design tradeoffs in Packet processing architectures
Design Automation Conference, 2002Co-Authors: Lothar Thiele, Samarjit Chakraborty, Matthias Gries, Simon KunzliAbstract:We present an analytical method to evaluate embedded network Packet Processor architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study.
Salvatore Pontarelli - One of the best experts on this subject based on the ideXlab platform.
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high speed data plane and network functions virtualization by vectorizing Packet processing
Computer Networks, 2019Co-Authors: Leonardo Linguaglossa, Salvatore Pontarelli, David Richard Barach, Dario Rossi, Damjan Marjon, Pierre PfisterAbstract:Abstract In the last decade, a number of frameworks started to appear that implement, directly in user-space with kernel-bypass mode, high-speed software data plane functionalities on commodity hardware. This may be the key to replace specific hardware-based middleboxes with custom pieces of software, as advocated by the recent Network Function Virtualization (NFV) paradigm. Vector Packet Processor (VPP) is one of such frameworks, representing an interesting point in the design space in that it offers: (i) in user-space networking, (ii) the flexibility of a modular router (Click and variants) with (iii) high-speed performance (several millions of Packets per second on a single CPU core), achieved through techniques such as batch processing that have become commonplace in high-speed networking stacks (e.g. netmap or DPDK). Similarly to Click, VPP lets users arrange functions as a processing graph, providing a full-blown stack of network functions. However, unlike Click where the whole tree is traversed for each Packet, in VPP each traversed node processes all Packets in the batch (or vector) before moving to the next node. This design choice enables several code optimizations that greatly improve the achievable throughput. This paper introduces the main VPP concepts and architecture, and experimentally evaluates the impact of its design choices (such as batch Packet processing) on its performance.
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TupleMerge: Fast Software Packet Processing for Online Packet Classification
IEEE ACM Transactions on Networking, 2019Co-Authors: James Daly, Salvatore Pontarelli, Leonardo Linguaglossa, Dario Rossi, Valerio Bruschi, Jerome Tollet, Eric Torng, Andrew YourtchenkoAbstract:Packet classification is an important part of many networking devices, such as routers and firewalls. Software-defined networking (SDN) heavily relies on online Packet classification which must efficiently process two different streams: incoming Packets to classify and rules to update. This rules out many offline Packet classification algorithms that do not support fast updates. We propose a novel online classification algorithm, TupleMerge (TM), derived from tuple space search (TSS), the Packet classifier used by Open vSwitch (OVS). TM improves upon TSS by combining hash tables which contain rules with similar characteristics. This greatly reduces classification time preserving similar performance in updates. We validate the effectiveness of TM using both simulation and deployment in a full-fledged software router, specifically within the vector Packet Processor (VPP). In our simulation results, which focus solely on the efficiency of the classification algorithm, we demonstrate that TM outperforms all other state of the art methods, including TSS, PartitionSort (PS), and SAX-PAC. For example, TM is 34% faster at classifying Packets and 30% faster at updating rules than PS. We then experimentally evaluate TM deployed within the VPP framework comparing TM against linear search and TSS, and also against TSS within the OVS framework. This validation of deployed implementations is important as SDN frameworks have several optimizations such as caches that may minimize the influence of a classification algorithm. Our experimental results clearly validate the effectiveness of TM. VPP TM classifies Packets nearly two orders of magnitude faster than VPP TSS and at least one order of magnitude faster than OVS TSS.
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high speed software data plane via vectorized Packet processing
IEEE Communications Magazine, 2018Co-Authors: David Richard Barach, Salvatore Pontarelli, Leonardo Linguaglossa, Damjan Marion, Pierre Pfister, Dario RossiAbstract:In the last decade, a number of frameworks started to appear that implement, directly in userspace with kernel-bypass mode, high-speed software data plane functionalities on commodity hardware. Vector Packet Processor (VPP) is one of such frameworks, representing an interesting point in the design space in that it offers, in userspace networking, the flexibility of a modular router (Click and variants), with the benefits provided by techniques such as batch processing that have become commonplace in high-speed networking stacks (such as netmap or DPDK). Similarly to Click, VPP lets users arrange functions as a processing graph, providing a full-blown stack of network functions. However, unlike Click, where the whole tree is traversed for each Packet, in VPP each traversed node processes all Packets in the batch (called vector) before moving to the next node. This design choice enables several code optimizations that greatly improve the achievable processing throughput. This article introduces the main VPP concepts and architecture, and experimentally evaluates the impact of design choices (such as batch Packet processing) on performance.
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open Packet Processor a programmable architecture for wire speed platform independent stateful in network processing
arXiv: Networking and Internet Architecture, 2016Co-Authors: Giuseppe Bianchi, Marco Bonola, Salvatore Pontarelli, Davide Sanvito, Antonio Capone, Carmelo CasconeAbstract:This paper aims at contributing to the ongoing debate on how to bring programmability of stateful Packet processing tasks inside the network switches, while retaining platform independency. Our proposed approach, named "Open Packet Processor" (OPP), shows the viability (via an hardware prototype relying on commodity HW technologies and operating in a strictly bounded number of clock cycles) of eXtended Finite State Machines (XFSM) as low-level data plane programming abstraction. With the help of examples, including a token bucket and a C4.5 traffic classifier based on a binary tree, we show the ability of OPP to support stateful operation and flow-level feature tracking. Platform independence is accomplished by decoupling the implementation of hardware primitives (registries, conditions, update instructions, forwarding actions, matching facilities) from their usage by an application formally described via an abstract XFSM. We finally discuss limitations and extensions.
Xianming Zhang - One of the best experts on this subject based on the ideXlab platform.
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event triggered dissipative control for networked stochastic systems under non uniform sampling
Information Sciences, 2018Co-Authors: Jia Wang, Xianming Zhang, Yufeng Lin, Qinglong HanAbstract:Abstract This paper is concerned with dissipative control for networked stochastic systems with an event-triggered transmission mechanism. Different from some existing results, signals from a physical plant are sampled non-uniformly . In order to save precious communication resources, a data-Packet Processor is introduced to choose necessary data-Packets based on a flexible event-triggered condition. By establishing an integral inequality in stochastic setting, which is regarded as a counterpart of Wirtinger-based inequality, a criterion is derived such that the resultant closed-loop system is mean-square stable and dissipative. This criterion is then used to calculate suitable event-triggered controllers in terms of solutions to linear matrix inequalities. An air vehicle system is finally taken to substantiate the validity of the proposed method.
-
a decentralized event triggered dissipative control scheme for systems with multiple sensors to sample the system outputs
IEEE Transactions on Systems Man and Cybernetics, 2016Co-Authors: Xianming Zhang, Qinglong HanAbstract:This paper is concerned with decentralized event-triggered dissipative control for systems with the entries of the system outputs having different physical properties. Depending on these different physical properties, the entries of the system outputs are grouped into multiple nodes. A number of sensors are used to sample the signals from different nodes. A decentralized event-triggering scheme is introduced to select those necessary sampled-data Packets to be transmitted so that communication resources can be saved significantly while preserving the prescribed closed-loop performance. First, in order to organize the decentralized data Packets transmitted from the sensor nodes, a data Packet Processor (DPP) is used to generate a new signal to be held by the zero-order-hold once the signal stored by the DPP is updated at some time instant. Second, under the mechanism of the DPP, the resulting closed-loop system is modeled as a linear system with an interval time-varying delay. A sufficient condition is derived such that the closed-loop system is asymptotically stable and strictly $ {(Q_{0},S_{0},R_{0})}$ -dissipative, where $ {Q_{0},S_{0}}$ , and $ {R_{0}}$ are real matrices of appropriate dimensions with $ {Q_{0}}$ and $ {R_{0}}$ symmetric. Third, suitable output-based controllers can be designed based on solutions to a set of a linear matrix inequality. Finally, two examples are given to demonstrate the effectiveness of the proposed method.
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event based h filtering for sampled data systems
Automatica, 2015Co-Authors: Xianming Zhang, Qinglong HanAbstract:This paper is concerned with event-based H ∞ filtering for sampled-data systems. First, an event-based data Packet Processor is introduced to release sampled measurement outputs only if an event condition is violated. As a result, communication resources can be saved significantly while preserving the desired H ∞ performance. Second, the resulting filtering error system is modeled as a system with an interval time-varying delay. By employing the Lyapunov-Krasovskii functional approach, a new bounded real lemma (BRL) is established such that the filtering error system is asymptotically stable with the prescribed H ∞ performance. Third, by performing an invertible linear transformation on the filtering error system, a linear matrix inequality (LMI)-based sufficient condition, which is equivalent to the condition in the BRL, is obtained on the feasibility of the event-based H ∞ filtering problem. Consequently, suitable H ∞ filters and the event parameters in the event condition can be co-designed provided that a set of LMIs are satisfied. Finally, a mechanical system with two masses and two springs is given to show the effectiveness of the proposed method.
