The Experts below are selected from a list of 74724 Experts worldwide ranked by ideXlab platform
George A Constantinides - One of the best experts on this subject based on the ideXlab platform.
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a Parallel Hardware architecture for scale and rotation invariant feature detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a Parallel Hardware architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific Hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several Hardware-orientated optimizations on performance, area and accuracy.
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a Parallel Hardware architecture for scale and rotation invariant feature detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a Parallel Hardware architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific Hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several Hardware-orientated optimizations on performance, area and accuracy.
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a Parallel Hardware architecture for image feature detection
Applied Reconfigurable Computing, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time Parallel Hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed Hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for Hardware implementation of the SIFT algorithm and proposes specific Hardware optimizations considered fundamental to embed whole system on a single chip, which implements in Parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.
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ARC - A Parallel Hardware Architecture for Image Feature Detection
Lecture Notes in Computer Science, 1Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time Parallel Hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed Hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for Hardware implementation of the SIFT algorithm and proposes specific Hardware optimizations considered fundamental to embed whole system on a single chip, which implements in Parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.
Vanderlei Bonato - One of the best experts on this subject based on the ideXlab platform.
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a Parallel Hardware architecture for scale and rotation invariant feature detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a Parallel Hardware architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific Hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several Hardware-orientated optimizations on performance, area and accuracy.
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a Parallel Hardware architecture for scale and rotation invariant feature detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a Parallel Hardware architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific Hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several Hardware-orientated optimizations on performance, area and accuracy.
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a Parallel Hardware architecture for image feature detection
Applied Reconfigurable Computing, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time Parallel Hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed Hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for Hardware implementation of the SIFT algorithm and proposes specific Hardware optimizations considered fundamental to embed whole system on a single chip, which implements in Parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.
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ARC - A Parallel Hardware Architecture for Image Feature Detection
Lecture Notes in Computer Science, 1Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time Parallel Hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed Hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for Hardware implementation of the SIFT algorithm and proposes specific Hardware optimizations considered fundamental to embed whole system on a single chip, which implements in Parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.
Eduardo Marques - One of the best experts on this subject based on the ideXlab platform.
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a Parallel Hardware architecture for scale and rotation invariant feature detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a Parallel Hardware architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific Hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several Hardware-orientated optimizations on performance, area and accuracy.
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a Parallel Hardware architecture for scale and rotation invariant feature detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a Parallel Hardware architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific Hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several Hardware-orientated optimizations on performance, area and accuracy.
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a Parallel Hardware architecture for image feature detection
Applied Reconfigurable Computing, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time Parallel Hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed Hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for Hardware implementation of the SIFT algorithm and proposes specific Hardware optimizations considered fundamental to embed whole system on a single chip, which implements in Parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.
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ARC - A Parallel Hardware Architecture for Image Feature Detection
Lecture Notes in Computer Science, 1Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time Parallel Hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed Hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for Hardware implementation of the SIFT algorithm and proposes specific Hardware optimizations considered fundamental to embed whole system on a single chip, which implements in Parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.
Jeff Z Pan - One of the best experts on this subject based on the ideXlab platform.
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rdfs reasoning on massively Parallel Hardware
International Semantic Web Conference, 2012Co-Authors: Norman Heino, Jeff Z PanAbstract:Recent developments in Hardware have shown an increase in Parallelism as opposed to clock rates. In order to fully exploit these new avenues of performance improvement, computationally expensive workloads have to be expressed in a way that allows for fine-grained Parallelism. In this paper, we address the problem of describing RDFS entailment in such a way. Different from previous work on Parallel RDFS reasoning, we assume a shared memory architecture. We analyze the problem of duplicates that naturally occur in RDFS reasoning and develop strategies towards its mitigation, exploiting all levels of our architecture. We implement and evaluate our approach on two real-world datasets and study its performance characteristics on different levels of Parallelization. We conclude that RDFS entailment lends itself well to Parallelization but can benefit even more from careful optimizations that take into account intricacies of modern Parallel Hardware.
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International Semantic Web Conference (1) - RDFS reasoning on massively Parallel Hardware
The Semantic Web – ISWC 2012, 2012Co-Authors: Norman Heino, Jeff Z PanAbstract:Recent developments in Hardware have shown an increase in Parallelism as opposed to clock rates. In order to fully exploit these new avenues of performance improvement, computationally expensive workloads have to be expressed in a way that allows for fine-grained Parallelism. In this paper, we address the problem of describing RDFS entailment in such a way. Different from previous work on Parallel RDFS reasoning, we assume a shared memory architecture. We analyze the problem of duplicates that naturally occur in RDFS reasoning and develop strategies towards its mitigation, exploiting all levels of our architecture. We implement and evaluate our approach on two real-world datasets and study its performance characteristics on different levels of Parallelization. We conclude that RDFS entailment lends itself well to Parallelization but can benefit even more from careful optimizations that take into account intricacies of modern Parallel Hardware.
Tamer Shanableh - One of the best experts on this subject based on the ideXlab platform.
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FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification
IEEE Transactions on Computational Imaging, 2015Co-Authors: Murad Qasaimeh, Assim Sagahyroon, Tamer ShanablehAbstract:This paper proposes a Parallel Hardware architecture for real-time image classification based on scale-invariant feature transform (SIFT), bag of features (BoFs), and support vector machine (SVM) algorithms. The proposed architecture exploits different forms of Parallelism in these algorithms in order to accelerate their execution to achieve real-time performance. Different techniques have been used to Parallelize the execution and reduce the Hardware resource utilization of the computationally intensive steps in these algorithms. The architecture takes a ${\mathbf {640}} \times {\mathbf {480}}$ pixel image as an input and classifies it based on its content within 33 ms. A prototype of the proposed architecture is implemented on an FPGA platform and evaluated using two benchmark datasets: 1) Caltech-256 and 2) the Belgium Traffic Sign datasets. The architecture is able to detect up to 1270 SIFT features per frame with an increment of 380 extra features from the best recent implementation. We were able to speedup the feature extraction algorithm when compared to an equivalent software implementation by ${\mathbf {54}} \times$ and for classification algorithm by ${\mathbf {6}} \times$ , while maintaining the difference in classification accuracy within 3%. The Hardware resources utilized by our architecture were also less than those used by other existing solutions.
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A Parallel Hardware Architecture for Scale Invariant Feature Transform (SIFT)
2014 International Conference on Multimedia Computing and Systems (ICMCS), 2014Co-Authors: Murad Qasaimeh, Assim Sagahyroon, Tamer ShanablehAbstract:Scale Invariant Feature Transform (SIFT) is an efficient algorithm for extracting distinctive features from images. It is used in many computer vision applications such as object recognition, motion estimation, robot mapping and navigation. Although it has an outstanding performance, its implementation requires extensive computations, and it is very difficult to achieve near real-time feature extraction using software implementation only. Hence, there is a clear advantage in exploring the feasibility of implementing the algorithm using customized Hardware with the intent of achieving real-time performance. In this paper, a Parallel Hardware architecture is proposed to accelerate the SIFT features extraction. The proposed approach is viable and yields promising results in terms of accuracy, speed, and Hardware resources.
