The Experts below are selected from a list of 321 Experts worldwide ranked by ideXlab platform
Junjie Yang - One of the best experts on this subject based on the ideXlab platform.
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Paralleling variable block size motion estimation of hevc on cpu plus gpu platform
International Conference on Multimedia and Expo, 2013Co-Authors: Xiangwen Wang, Li Song, Min Chen, Junjie YangAbstract:The emerging HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 to conduct motion estimation (ME) and motion compensation (MC). This feature contributes considerable coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. In the test model HM, ME with variable block sizes (VBSME) may be called up to 425 times for the mode decision procedure of one CTU (Coding Tree Unit). Obviously, VBSME becomes the bottleneck for real time encoding. In this paper, we focus on Parallel Realization architecture design of VBSME in HEVC. Firstly, an efficient Parallel encoder framework is proposed for CPU plus GPU platform. With the framework, VBSME, fractional-pixel image interpolation and border padding processes run on GPU without burden on the host CPU. Secondly, for workload balance between CPU and GPU, a fast Prediction Unit partition mode decision algorithm is also proposed. Lastly, the Parallel Realization strategy of VBSME on GPU is improved for ME compression performance improvement. Experimental results based on the NVIDIA's C2050 GPU show that the speed of the VBSME strategy on GPU is about 113 times faster than the one on CPU.
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ICME Workshops - Paralleling variable block size motion estimation of HEVC on CPU plus GPU platform
2013 IEEE International Conference on Multimedia and Expo Workshops (ICMEW), 2013Co-Authors: Xiangwen Wang, Li Song, Min Chen, Junjie YangAbstract:The emerging HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 to conduct motion estimation (ME) and motion compensation (MC). This feature contributes considerable coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. In the test model HM, ME with variable block sizes (VBSME) may be called up to 425 times for the mode decision procedure of one CTU (Coding Tree Unit). Obviously, VBSME becomes the bottleneck for real time encoding. In this paper, we focus on Parallel Realization architecture design of VBSME in HEVC. Firstly, an efficient Parallel encoder framework is proposed for CPU plus GPU platform. With the framework, VBSME, fractional-pixel image interpolation and border padding processes run on GPU without burden on the host CPU. Secondly, for workload balance between CPU and GPU, a fast Prediction Unit partition mode decision algorithm is also proposed. Lastly, the Parallel Realization strategy of VBSME on GPU is improved for ME compression performance improvement. Experimental results based on the NVIDIA's C2050 GPU show that the speed of the VBSME strategy on GPU is about 113 times faster than the one on CPU.
Xiangwen Wang - One of the best experts on this subject based on the ideXlab platform.
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Paralleling variable block size motion estimation of hevc on cpu plus gpu platform
International Conference on Multimedia and Expo, 2013Co-Authors: Xiangwen Wang, Li Song, Min Chen, Junjie YangAbstract:The emerging HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 to conduct motion estimation (ME) and motion compensation (MC). This feature contributes considerable coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. In the test model HM, ME with variable block sizes (VBSME) may be called up to 425 times for the mode decision procedure of one CTU (Coding Tree Unit). Obviously, VBSME becomes the bottleneck for real time encoding. In this paper, we focus on Parallel Realization architecture design of VBSME in HEVC. Firstly, an efficient Parallel encoder framework is proposed for CPU plus GPU platform. With the framework, VBSME, fractional-pixel image interpolation and border padding processes run on GPU without burden on the host CPU. Secondly, for workload balance between CPU and GPU, a fast Prediction Unit partition mode decision algorithm is also proposed. Lastly, the Parallel Realization strategy of VBSME on GPU is improved for ME compression performance improvement. Experimental results based on the NVIDIA's C2050 GPU show that the speed of the VBSME strategy on GPU is about 113 times faster than the one on CPU.
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ICME Workshops - Paralleling variable block size motion estimation of HEVC on CPU plus GPU platform
2013 IEEE International Conference on Multimedia and Expo Workshops (ICMEW), 2013Co-Authors: Xiangwen Wang, Li Song, Min Chen, Junjie YangAbstract:The emerging HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 to conduct motion estimation (ME) and motion compensation (MC). This feature contributes considerable coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. In the test model HM, ME with variable block sizes (VBSME) may be called up to 425 times for the mode decision procedure of one CTU (Coding Tree Unit). Obviously, VBSME becomes the bottleneck for real time encoding. In this paper, we focus on Parallel Realization architecture design of VBSME in HEVC. Firstly, an efficient Parallel encoder framework is proposed for CPU plus GPU platform. With the framework, VBSME, fractional-pixel image interpolation and border padding processes run on GPU without burden on the host CPU. Secondly, for workload balance between CPU and GPU, a fast Prediction Unit partition mode decision algorithm is also proposed. Lastly, the Parallel Realization strategy of VBSME on GPU is improved for ME compression performance improvement. Experimental results based on the NVIDIA's C2050 GPU show that the speed of the VBSME strategy on GPU is about 113 times faster than the one on CPU.
Min Chen - One of the best experts on this subject based on the ideXlab platform.
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Paralleling variable block size motion estimation of hevc on cpu plus gpu platform
International Conference on Multimedia and Expo, 2013Co-Authors: Xiangwen Wang, Li Song, Min Chen, Junjie YangAbstract:The emerging HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 to conduct motion estimation (ME) and motion compensation (MC). This feature contributes considerable coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. In the test model HM, ME with variable block sizes (VBSME) may be called up to 425 times for the mode decision procedure of one CTU (Coding Tree Unit). Obviously, VBSME becomes the bottleneck for real time encoding. In this paper, we focus on Parallel Realization architecture design of VBSME in HEVC. Firstly, an efficient Parallel encoder framework is proposed for CPU plus GPU platform. With the framework, VBSME, fractional-pixel image interpolation and border padding processes run on GPU without burden on the host CPU. Secondly, for workload balance between CPU and GPU, a fast Prediction Unit partition mode decision algorithm is also proposed. Lastly, the Parallel Realization strategy of VBSME on GPU is improved for ME compression performance improvement. Experimental results based on the NVIDIA's C2050 GPU show that the speed of the VBSME strategy on GPU is about 113 times faster than the one on CPU.
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ICME Workshops - Paralleling variable block size motion estimation of HEVC on CPU plus GPU platform
2013 IEEE International Conference on Multimedia and Expo Workshops (ICMEW), 2013Co-Authors: Xiangwen Wang, Li Song, Min Chen, Junjie YangAbstract:The emerging HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 to conduct motion estimation (ME) and motion compensation (MC). This feature contributes considerable coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. In the test model HM, ME with variable block sizes (VBSME) may be called up to 425 times for the mode decision procedure of one CTU (Coding Tree Unit). Obviously, VBSME becomes the bottleneck for real time encoding. In this paper, we focus on Parallel Realization architecture design of VBSME in HEVC. Firstly, an efficient Parallel encoder framework is proposed for CPU plus GPU platform. With the framework, VBSME, fractional-pixel image interpolation and border padding processes run on GPU without burden on the host CPU. Secondly, for workload balance between CPU and GPU, a fast Prediction Unit partition mode decision algorithm is also proposed. Lastly, the Parallel Realization strategy of VBSME on GPU is improved for ME compression performance improvement. Experimental results based on the NVIDIA's C2050 GPU show that the speed of the VBSME strategy on GPU is about 113 times faster than the one on CPU.
Li Song - One of the best experts on this subject based on the ideXlab platform.
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Paralleling variable block size motion estimation of hevc on cpu plus gpu platform
International Conference on Multimedia and Expo, 2013Co-Authors: Xiangwen Wang, Li Song, Min Chen, Junjie YangAbstract:The emerging HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 to conduct motion estimation (ME) and motion compensation (MC). This feature contributes considerable coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. In the test model HM, ME with variable block sizes (VBSME) may be called up to 425 times for the mode decision procedure of one CTU (Coding Tree Unit). Obviously, VBSME becomes the bottleneck for real time encoding. In this paper, we focus on Parallel Realization architecture design of VBSME in HEVC. Firstly, an efficient Parallel encoder framework is proposed for CPU plus GPU platform. With the framework, VBSME, fractional-pixel image interpolation and border padding processes run on GPU without burden on the host CPU. Secondly, for workload balance between CPU and GPU, a fast Prediction Unit partition mode decision algorithm is also proposed. Lastly, the Parallel Realization strategy of VBSME on GPU is improved for ME compression performance improvement. Experimental results based on the NVIDIA's C2050 GPU show that the speed of the VBSME strategy on GPU is about 113 times faster than the one on CPU.
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ICME Workshops - Paralleling variable block size motion estimation of HEVC on CPU plus GPU platform
2013 IEEE International Conference on Multimedia and Expo Workshops (ICMEW), 2013Co-Authors: Xiangwen Wang, Li Song, Min Chen, Junjie YangAbstract:The emerging HEVC standard supports up to 12 variable block sizes ranging from 4×8/8×4 to 64×64 to conduct motion estimation (ME) and motion compensation (MC). This feature contributes considerable coding gain compared with 7 variable block sizes in H.264/AVC at the cost of huge computational complexity. In the test model HM, ME with variable block sizes (VBSME) may be called up to 425 times for the mode decision procedure of one CTU (Coding Tree Unit). Obviously, VBSME becomes the bottleneck for real time encoding. In this paper, we focus on Parallel Realization architecture design of VBSME in HEVC. Firstly, an efficient Parallel encoder framework is proposed for CPU plus GPU platform. With the framework, VBSME, fractional-pixel image interpolation and border padding processes run on GPU without burden on the host CPU. Secondly, for workload balance between CPU and GPU, a fast Prediction Unit partition mode decision algorithm is also proposed. Lastly, the Parallel Realization strategy of VBSME on GPU is improved for ME compression performance improvement. Experimental results based on the NVIDIA's C2050 GPU show that the speed of the VBSME strategy on GPU is about 113 times faster than the one on CPU.
Piotr Ostalczyk - One of the best experts on this subject based on the ideXlab platform.
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ECC - Parallel Realization of the variable-, fractional-order difference equation
2019 18th European Control Conference (ECC), 2019Co-Authors: Piotr OstalczykAbstract:In the paper a block–matrix form of the variable–, fractional–order linear time–invariant difference equation is investigated. It is proved that similar to the state–space representation but with linearly increasing matrix–vector dimensions is useful in the difference equation solution. The block diagram of the system is described by the Jordan–like canonical form. It uses the variable–, fractional–order integrators and proportional blocks. The proposed approach simplifies numerical calculations of solutions due to a possibility of Parallel computations. Analysis is supported by the numerical example.
