The Experts below are selected from a list of 174 Experts worldwide ranked by ideXlab platform
Xiaozhi Zhang - One of the best experts on this subject based on the ideXlab platform.
-
Design and development of a new 3-DOF active-type constant-force compliant Parallel Stage
Mechanism and Machine Theory, 2019Co-Authors: Xiaozhi ZhangAbstract:Abstract This paper presents the design, development, and testing of a novel three-degree-of-freedom compliant Parallel-kinematic active constant-force Stage. The active constant-force property enables a large travel and constant driving property, which is enabled by introducing symmetrical bistable flexure hinges. The folded flexure mechanism is adopted to guide the driving input and to balance the stiffness of the Stage to zero. Besides, leaf flexure hinges are employed to decouple the cross-axis motion of the three-degree-of-freedom Parallel Stage. Analytical modeling is conducted to evaluate the Stage performances of constant-force property and motion decoupling, which is verified by performing finite-element analysis simulation study. Design optimization of the Stage parameters is implemented for minimizing the fluctuation of the constant-force value via multi-objective genetic algorithm. Moreover, a prototype is fabricated and experimental study is carried out to validate the analytical modeling results and performances of the proposed Stage design.
-
IROS - Design and Analysis of a New 3-DOF Active-Type Constant-Force Compliant Parallel Stage
2019 IEEE RSJ International Conference on Intelligent Robots and Systems (IROS), 2019Co-Authors: Xiaozhi Zhang, Yuzhang WeiAbstract:This paper presents the design, analysis and testing of a novel three-degree-of-freedom (3-DOF) compliant Parallel-kinematic active constant-force Stage. The active constant-force property enables a large travel and constant driving property, which is enabled by introducing symmetrical bistable flexure hinges. The folded flexure mechanism is adopted to guide the driving input and to balance the stiffness of the Stage to zero. In addition, leaf flexure hinges are employed to decouple the cross-axis motion of the 3-DOF Parallel Stage. Analytical modeling is conducted to evaluate the Stage performance. To verify the performance of the constant-force property and motion decoupling, finite-element analysis simulation study is carried out. By minimizing the fluctuation of the constant-force value, design optimization of the Stage parameters is implemented with multi-objective genetic algorithm. Moreover, a prototype is fabricated for demonstration of the proposed concept design.
-
Design, fabrication and testing of a novel symmetrical 3-DOF large-stroke Parallel micro/nano-positioning Stage
Robotics and Computer-Integrated Manufacturing, 2018Co-Authors: Xiaozhi ZhangAbstract:Abstract Limited travel stroke constrains the application of existing XYZ Parallel micro/nano-positioning Stages. In this paper, a novel Parallel-kinematic symmetrical micro/nano-positioning Stage is proposed to enlarge the travel range with a compact physical size. For a large-stroke Parallel Stage, the cross-axis motion increases the difficulty of closed-loop control process. The motions of the Parallel Stage on different axes are decoupled by employing I-shaped flexure hinges in this work. In order to obtain a large input displacement for actuating the Stage, three voice coil motors (VCM) are adopted. In view of the lower output force of the VCM, the guiding flexure mechanism is designed with an optimized cross-sectional dimension. To verify the performance of the Stage, analytical modeling and simulation study are carried out. A prototype Stage is fabricated for experimental studies. Results show that the designed Parallel micro/nano-positioning Stage owns a three-degree-of-freedom motion workspace of 2.22 mm × 2.22 mm × 1.81 mm with an overall size of 176 mm × 176 mm × 198 mm, which is more compact than existing symmetrical designs containing the actuators. Moreover, the symmetrical design enables a low crosstalk of 1.7% among the three working axes.
-
design fabrication and testing of a novel symmetrical 3 dof large stroke Parallel micro nano positioning Stage
Robotics and Computer-integrated Manufacturing, 2017Co-Authors: Xiaozhi ZhangAbstract:Abstract Limited travel stroke constrains the application of existing XYZ Parallel micro/nano-positioning Stages. In this paper, a novel Parallel-kinematic symmetrical micro/nano-positioning Stage is proposed to enlarge the travel range with a compact physical size. For a large-stroke Parallel Stage, the cross-axis motion increases the difficulty of closed-loop control process. The motions of the Parallel Stage on different axes are decoupled by employing I-shaped flexure hinges in this work. In order to obtain a large input displacement for actuating the Stage, three voice coil motors (VCM) are adopted. In view of the lower output force of the VCM, the guiding flexure mechanism is designed with an optimized cross-sectional dimension. To verify the performance of the Stage, analytical modeling and simulation study are carried out. A prototype Stage is fabricated for experimental studies. Results show that the designed Parallel micro/nano-positioning Stage owns a three-degree-of-freedom motion workspace of 2.22 mm × 2.22 mm × 1.81 mm with an overall size of 176 mm × 176 mm × 198 mm, which is more compact than existing symmetrical designs containing the actuators. Moreover, the symmetrical design enables a low crosstalk of 1.7% among the three working axes.
-
IECON - Design and modeling of a novel 3-DOF large-travel Parallel micro/nano-positioning Stage
IECON 2017 - 43rd Annual Conference of the IEEE Industrial Electronics Society, 2017Co-Authors: Xiaozhi ZhangAbstract:Limited travel constrains the widely application of XYZ Parallel micro/nano-positioning Stage. In this paper, a novel Parallel-kinematics micro/nano-positioning Stage is proposed with the goal of enlarging the travel range. In order to obtain a large input displacement for actuating the Stage, voice coil motors (VCM) are adopted. For a large-travel Parallel Stage, the cross-axis motion increases the difficulty of closed-loop control process. Thus, the I-shaped flexure hinges are employed to decouple the Parallel Stage's motion. In view of the lower output force of the VCM, the guiding flexure mechanism is designed with an optimized sectional dimension of 140 mm × 44 mm. To verify the performance of the Stage, analytical modeling and simulation study are conducted. Results show that the proposed large-travel Parallel micro/nano-positioning Stage owns the 3-DOF motion range of 3.527 mm, an oversize of 176 mm × 176 mm × 198 mm, and negligible isolation ratio of 0.0034%.
Yuzhang Wei - One of the best experts on this subject based on the ideXlab platform.
-
IROS - Design and Analysis of a New 3-DOF Active-Type Constant-Force Compliant Parallel Stage
2019 IEEE RSJ International Conference on Intelligent Robots and Systems (IROS), 2019Co-Authors: Xiaozhi Zhang, Yuzhang WeiAbstract:This paper presents the design, analysis and testing of a novel three-degree-of-freedom (3-DOF) compliant Parallel-kinematic active constant-force Stage. The active constant-force property enables a large travel and constant driving property, which is enabled by introducing symmetrical bistable flexure hinges. The folded flexure mechanism is adopted to guide the driving input and to balance the stiffness of the Stage to zero. In addition, leaf flexure hinges are employed to decouple the cross-axis motion of the 3-DOF Parallel Stage. Analytical modeling is conducted to evaluate the Stage performance. To verify the performance of the constant-force property and motion decoupling, finite-element analysis simulation study is carried out. By minimizing the fluctuation of the constant-force value, design optimization of the Stage parameters is implemented with multi-objective genetic algorithm. Moreover, a prototype is fabricated for demonstration of the proposed concept design.
David I August - One of the best experts on this subject based on the ideXlab platform.
-
Parallel Stage decoupled software pipelining
Symposium on Code Generation and Optimization, 2008Co-Authors: Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J Bridges, David I AugustAbstract:In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and new applications to make effective use of CMPs, it is desirable that compilers automatically extract thread-level Parallelism from single-threaded applications. DOALL is a popular automatic technique for loop-level Parallelization employed successfully in the domains of scientific and numeric computing. While DOALL generally scales well with the number of iterations of the loop, its applicability is limited by the presence of loop-carried dependences. A Parallelization technique with greater applicability is decoupled software pipelining (DSWP), which Parallelizes loops even in the presence of loop-carried dependences. However, the scalability of DSWP is limited by the size of the loop body and the number of recurrences it contains, which are usually smaller than the loop iteration count. This work proposes a novel non-speculative compiler Parallelization technique called Parallel-Stage decoupled software pipelining (PS-DSWP). The goal of PS-DSWP is to combine the applicability of DSWP with the scalability of DOALL Parallelization. A key insight of PS-DSWP is that, after isolating the recurrences in their own Stages in DSWP, portions of the loop suitable for DOALL Parallelization may be exposed. PS-DSWP extends DSWP to benefit from these opportunities, utilizing multiple threads to execute the same Stage of a DSWPed loop in Parallel. This paper describes the PS-DSWP transformation in detail and discusses its implementation in a research compiler. PS-DSWP produces an average speedup of 114% (up to a maximum of 155%) with 6 threads on loops from a set of 5 applications. Our experiments also demonstrate that PS-DSWP achieves better scalability with the number of threads than DSWP.
-
CGO - Parallel-Stage decoupled software pipelining
Proceedings of the sixth annual IEEE ACM international symposium on Code generation and optimization - CGO '08, 2008Co-Authors: Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J Bridges, David I AugustAbstract:In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and new applications to make effective use of CMPs, it is desirable that compilers automatically extract thread-level Parallelism from single-threaded applications. DOALL is a popular automatic technique for loop-level Parallelization employed successfully in the domains of scientific and numeric computing. While DOALL generally scales well with the number of iterations of the loop, its applicability is limited by the presence of loop-carried dependences. A Parallelization technique with greater applicability is decoupled software pipelining (DSWP), which Parallelizes loops even in the presence of loop-carried dependences. However, the scalability of DSWP is limited by the size of the loop body and the number of recurrences it contains, which are usually smaller than the loop iteration count. This work proposes a novel non-speculative compiler Parallelization technique called Parallel-Stage decoupled software pipelining (PS-DSWP). The goal of PS-DSWP is to combine the applicability of DSWP with the scalability of DOALL Parallelization. A key insight of PS-DSWP is that, after isolating the recurrences in their own Stages in DSWP, portions of the loop suitable for DOALL Parallelization may be exposed. PS-DSWP extends DSWP to benefit from these opportunities, utilizing multiple threads to execute the same Stage of a DSWPed loop in Parallel. This paper describes the PS-DSWP transformation in detail and discusses its implementation in a research compiler. PS-DSWP produces an average speedup of 114% (up to a maximum of 155%) with 6 threads on loops from a set of 5 applications. Our experiments also demonstrate that PS-DSWP achieves better scalability with the number of threads than DSWP.
Easwaran Raman - One of the best experts on this subject based on the ideXlab platform.
-
Parallel Stage decoupled software pipelining
Symposium on Code Generation and Optimization, 2008Co-Authors: Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J Bridges, David I AugustAbstract:In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and new applications to make effective use of CMPs, it is desirable that compilers automatically extract thread-level Parallelism from single-threaded applications. DOALL is a popular automatic technique for loop-level Parallelization employed successfully in the domains of scientific and numeric computing. While DOALL generally scales well with the number of iterations of the loop, its applicability is limited by the presence of loop-carried dependences. A Parallelization technique with greater applicability is decoupled software pipelining (DSWP), which Parallelizes loops even in the presence of loop-carried dependences. However, the scalability of DSWP is limited by the size of the loop body and the number of recurrences it contains, which are usually smaller than the loop iteration count. This work proposes a novel non-speculative compiler Parallelization technique called Parallel-Stage decoupled software pipelining (PS-DSWP). The goal of PS-DSWP is to combine the applicability of DSWP with the scalability of DOALL Parallelization. A key insight of PS-DSWP is that, after isolating the recurrences in their own Stages in DSWP, portions of the loop suitable for DOALL Parallelization may be exposed. PS-DSWP extends DSWP to benefit from these opportunities, utilizing multiple threads to execute the same Stage of a DSWPed loop in Parallel. This paper describes the PS-DSWP transformation in detail and discusses its implementation in a research compiler. PS-DSWP produces an average speedup of 114% (up to a maximum of 155%) with 6 threads on loops from a set of 5 applications. Our experiments also demonstrate that PS-DSWP achieves better scalability with the number of threads than DSWP.
-
CGO - Parallel-Stage decoupled software pipelining
Proceedings of the sixth annual IEEE ACM international symposium on Code generation and optimization - CGO '08, 2008Co-Authors: Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J Bridges, David I AugustAbstract:In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and new applications to make effective use of CMPs, it is desirable that compilers automatically extract thread-level Parallelism from single-threaded applications. DOALL is a popular automatic technique for loop-level Parallelization employed successfully in the domains of scientific and numeric computing. While DOALL generally scales well with the number of iterations of the loop, its applicability is limited by the presence of loop-carried dependences. A Parallelization technique with greater applicability is decoupled software pipelining (DSWP), which Parallelizes loops even in the presence of loop-carried dependences. However, the scalability of DSWP is limited by the size of the loop body and the number of recurrences it contains, which are usually smaller than the loop iteration count. This work proposes a novel non-speculative compiler Parallelization technique called Parallel-Stage decoupled software pipelining (PS-DSWP). The goal of PS-DSWP is to combine the applicability of DSWP with the scalability of DOALL Parallelization. A key insight of PS-DSWP is that, after isolating the recurrences in their own Stages in DSWP, portions of the loop suitable for DOALL Parallelization may be exposed. PS-DSWP extends DSWP to benefit from these opportunities, utilizing multiple threads to execute the same Stage of a DSWPed loop in Parallel. This paper describes the PS-DSWP transformation in detail and discusses its implementation in a research compiler. PS-DSWP produces an average speedup of 114% (up to a maximum of 155%) with 6 threads on loops from a set of 5 applications. Our experiments also demonstrate that PS-DSWP achieves better scalability with the number of threads than DSWP.
Matthew J Bridges - One of the best experts on this subject based on the ideXlab platform.
-
Parallel Stage decoupled software pipelining
Symposium on Code Generation and Optimization, 2008Co-Authors: Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J Bridges, David I AugustAbstract:In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and new applications to make effective use of CMPs, it is desirable that compilers automatically extract thread-level Parallelism from single-threaded applications. DOALL is a popular automatic technique for loop-level Parallelization employed successfully in the domains of scientific and numeric computing. While DOALL generally scales well with the number of iterations of the loop, its applicability is limited by the presence of loop-carried dependences. A Parallelization technique with greater applicability is decoupled software pipelining (DSWP), which Parallelizes loops even in the presence of loop-carried dependences. However, the scalability of DSWP is limited by the size of the loop body and the number of recurrences it contains, which are usually smaller than the loop iteration count. This work proposes a novel non-speculative compiler Parallelization technique called Parallel-Stage decoupled software pipelining (PS-DSWP). The goal of PS-DSWP is to combine the applicability of DSWP with the scalability of DOALL Parallelization. A key insight of PS-DSWP is that, after isolating the recurrences in their own Stages in DSWP, portions of the loop suitable for DOALL Parallelization may be exposed. PS-DSWP extends DSWP to benefit from these opportunities, utilizing multiple threads to execute the same Stage of a DSWPed loop in Parallel. This paper describes the PS-DSWP transformation in detail and discusses its implementation in a research compiler. PS-DSWP produces an average speedup of 114% (up to a maximum of 155%) with 6 threads on loops from a set of 5 applications. Our experiments also demonstrate that PS-DSWP achieves better scalability with the number of threads than DSWP.
-
CGO - Parallel-Stage decoupled software pipelining
Proceedings of the sixth annual IEEE ACM international symposium on Code generation and optimization - CGO '08, 2008Co-Authors: Easwaran Raman, Guilherme Ottoni, Arun Raman, Matthew J Bridges, David I AugustAbstract:In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and new applications to make effective use of CMPs, it is desirable that compilers automatically extract thread-level Parallelism from single-threaded applications. DOALL is a popular automatic technique for loop-level Parallelization employed successfully in the domains of scientific and numeric computing. While DOALL generally scales well with the number of iterations of the loop, its applicability is limited by the presence of loop-carried dependences. A Parallelization technique with greater applicability is decoupled software pipelining (DSWP), which Parallelizes loops even in the presence of loop-carried dependences. However, the scalability of DSWP is limited by the size of the loop body and the number of recurrences it contains, which are usually smaller than the loop iteration count. This work proposes a novel non-speculative compiler Parallelization technique called Parallel-Stage decoupled software pipelining (PS-DSWP). The goal of PS-DSWP is to combine the applicability of DSWP with the scalability of DOALL Parallelization. A key insight of PS-DSWP is that, after isolating the recurrences in their own Stages in DSWP, portions of the loop suitable for DOALL Parallelization may be exposed. PS-DSWP extends DSWP to benefit from these opportunities, utilizing multiple threads to execute the same Stage of a DSWPed loop in Parallel. This paper describes the PS-DSWP transformation in detail and discusses its implementation in a research compiler. PS-DSWP produces an average speedup of 114% (up to a maximum of 155%) with 6 threads on loops from a set of 5 applications. Our experiments also demonstrate that PS-DSWP achieves better scalability with the number of threads than DSWP.
