The Experts below are selected from a list of 9 Experts worldwide ranked by ideXlab platform

Robert J. Hall - One of the best experts on this subject based on the ideXlab platform.

  • ASE - Validating Real Time Specifications using Real Time Event Queue Modeling
    2008 23rd IEEE ACM International Conference on Automated Software Engineering, 2008
    Co-Authors: Robert J. Hall
    Abstract:

    Interrupt-driven real time control software is difficult to design and validate. It does not line up well with traditional state-based, timed-transition specification formalisms, due to the complexity of timers and the Pending Interrupt queue. The present work takes a new approach to the problem of modeling and tool-supported reasoning about such systems based on infinite-state modeling of the temporal event queue. This approach, RTEQ, can be used in any formalism or tool set supporting function rich modeling. The present paper describes the approach, explores its expressive power and semantics, and describes a significant industrial case study applying it to the design of a novel network medium access controller for wireless communications.

  • ASE - Rteq: modeling and validating infinite-state hard-real-time systems
    Proceedings of the twenty-second IEEE ACM international conference on Automated software engineering - ASE '07, 2007
    Co-Authors: Robert J. Hall
    Abstract:

    Complex, Interrupt-driven hard real time control software is difficult to design and validate. It does not line up well with traditional state-based, timed-transition approaches to real time system specification, due to the complexity of timers and the Pending Interrupt queue. The present work takes a new approach to the problem of modeling and tool-supported reasoning about such systems based on infinite-state modeling of the temporal event queue. This approach, RTEQ, can be used in any formalism or tool set supporting event queue modeling. This paper briefly overviews the approach and its application to a novel wireless medium access controller

J. Nurmi - One of the best experts on this subject based on the ideXlab platform.

  • SoC - xICU - in Interrupt control unit for a configurable DSP core
    Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748), 1
    Co-Authors: C. Panis, J. Hohl, H. Gruenbacher, J. Nurmi
    Abstract:

    Increasing complexity of SoC applications leads to a strong demand on powerful software programmable embedded cores. Low-cost applications do not allow adding more than one core to the application. DePending on the application a DSP or a microcontroller is used. Therefore DSP cores have to handle Interrupts typically served by microcontroller sub-systems also with low latency and small overhead concerning cycle count and code density. This paper describes the architecture of an ICU (Interrupt control unit) for a configurable DSP core. The main architectural features of the ICU can be configured to reduce the consumed silicon area to an application specific optimum. Priority morphing is introduced to enable the control of the execution order of Pending Interrupt sources during run-time and to prevent the loss of Interrupt information. A smooth integration into the program sequencer allows short Interrupt latency and low overhead for serving ISRs (Interrupt service routines). xICU is a part of a configurable DSP core.

C. Panis - One of the best experts on this subject based on the ideXlab platform.

  • SoC - xICU - in Interrupt control unit for a configurable DSP core
    Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748), 1
    Co-Authors: C. Panis, J. Hohl, H. Gruenbacher, J. Nurmi
    Abstract:

    Increasing complexity of SoC applications leads to a strong demand on powerful software programmable embedded cores. Low-cost applications do not allow adding more than one core to the application. DePending on the application a DSP or a microcontroller is used. Therefore DSP cores have to handle Interrupts typically served by microcontroller sub-systems also with low latency and small overhead concerning cycle count and code density. This paper describes the architecture of an ICU (Interrupt control unit) for a configurable DSP core. The main architectural features of the ICU can be configured to reduce the consumed silicon area to an application specific optimum. Priority morphing is introduced to enable the control of the execution order of Pending Interrupt sources during run-time and to prevent the loss of Interrupt information. A smooth integration into the program sequencer allows short Interrupt latency and low overhead for serving ISRs (Interrupt service routines). xICU is a part of a configurable DSP core.

J. Hohl - One of the best experts on this subject based on the ideXlab platform.

  • SoC - xICU - in Interrupt control unit for a configurable DSP core
    Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748), 1
    Co-Authors: C. Panis, J. Hohl, H. Gruenbacher, J. Nurmi
    Abstract:

    Increasing complexity of SoC applications leads to a strong demand on powerful software programmable embedded cores. Low-cost applications do not allow adding more than one core to the application. DePending on the application a DSP or a microcontroller is used. Therefore DSP cores have to handle Interrupts typically served by microcontroller sub-systems also with low latency and small overhead concerning cycle count and code density. This paper describes the architecture of an ICU (Interrupt control unit) for a configurable DSP core. The main architectural features of the ICU can be configured to reduce the consumed silicon area to an application specific optimum. Priority morphing is introduced to enable the control of the execution order of Pending Interrupt sources during run-time and to prevent the loss of Interrupt information. A smooth integration into the program sequencer allows short Interrupt latency and low overhead for serving ISRs (Interrupt service routines). xICU is a part of a configurable DSP core.

H. Gruenbacher - One of the best experts on this subject based on the ideXlab platform.

  • SoC - xICU - in Interrupt control unit for a configurable DSP core
    Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748), 1
    Co-Authors: C. Panis, J. Hohl, H. Gruenbacher, J. Nurmi
    Abstract:

    Increasing complexity of SoC applications leads to a strong demand on powerful software programmable embedded cores. Low-cost applications do not allow adding more than one core to the application. DePending on the application a DSP or a microcontroller is used. Therefore DSP cores have to handle Interrupts typically served by microcontroller sub-systems also with low latency and small overhead concerning cycle count and code density. This paper describes the architecture of an ICU (Interrupt control unit) for a configurable DSP core. The main architectural features of the ICU can be configured to reduce the consumed silicon area to an application specific optimum. Priority morphing is introduced to enable the control of the execution order of Pending Interrupt sources during run-time and to prevent the loss of Interrupt information. A smooth integration into the program sequencer allows short Interrupt latency and low overhead for serving ISRs (Interrupt service routines). xICU is a part of a configurable DSP core.