The Experts below are selected from a list of 42420 Experts worldwide ranked by ideXlab platform
Byeongsoo Jeong - One of the best experts on this subject based on the ideXlab platform.
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Performance Bottleneck of subsequence matching in time-series databases: Observation, solution, and Performance evaluation
Information Sciences, 2007Co-Authors: Sangwook Kim, Byeongsoo JeongAbstract:Abstract Subsequence matching is an operation that finds subsequences whose changing patterns are similar to a given query sequence from time-series databases. This paper identifies a Performance Bottleneck in subsequence matching, and then proposes an effective method that substantially improves the Performance of entire subsequence matching by resolving the Performance Bottleneck. First, we analyze the disk access and CPU processing times required during the index searching and post-processing steps of subsequence matching through preliminary experiments. Based on these results, we show that the post-processing step is a main Performance Bottleneck in subsequence matching. Then, we argue that the optimization of the post-processing step is a crucial issue overlooked in previous approaches. In order to resolve the Performance Bottleneck, we propose a simple yet highly effective method for expediting the post-processing step. By rearranging the order of candidate subsequences to be compared with a query sequence, our method completely eliminates the redundancies of disk accesses and CPU processing that occur in the post-processing step. Our method is fairly efficient, and does not incur any false dismissal. We quantitatively demonstrate the superiority of our method through extensive experimentation. The results show that our method produces a significantly faster post-processing step; When using a data set of real-world stock sequences, our method was 43.36–96.75 times faster than previous methods, and when using data sets of large numbers of synthetic sequences, our method was 12.48–26.95 times faster than previous methods. Also, the results show that our method reduces the weight of the post-processing step over entire subsequence matching from more than 97% to less than 67%. This implies that our method successfully resolves the Performance Bottleneck in subsequence matching. As a result, our method provides excellent Performance in entire subsequence matching. Compared with previous methods, our method is 16.17–32.64 times faster when using a data set of real-world stock sequences and 8.64–14.29 times faster when using data sets of large numbers of synthetic sequences.
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Performance Bottleneck in time series subsequence matching
ACM Symposium on Applied Computing, 2005Co-Authors: Sangwook Kim, Byeongsoo JeongAbstract:This paper addresses a Performance Bottleneck in time-series subsequence matching. First, we analyze the disk access and CPU processing times required during the index searching and post-processing steps of subsequence matching through preliminary experiments. Based on their results, we show that the post-processing step is a main Performance Bottleneck in subsequence matching. In order to resolve the Performance Bottleneck, we propose a simple yet quite effective method that processes the post-processing step. By rearranging the order of candidate subsequences to be compared with a query sequence, our method completely eliminates the redundancies of disk accesses and CPU processing occurring in the post-processing step. We show that our method is optimal and also does not incur any false dismissal. Also, we justify the effectiveness of our method by extensive experiments.
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SAC - Performance Bottleneck in time-series subsequence matching
Proceedings of the 2005 ACM symposium on Applied computing - SAC '05, 2005Co-Authors: Sangwook Kim, Byeongsoo JeongAbstract:This paper addresses a Performance Bottleneck in time-series subsequence matching. First, we analyze the disk access and CPU processing times required during the index searching and post-processing steps of subsequence matching through preliminary experiments. Based on their results, we show that the post-processing step is a main Performance Bottleneck in subsequence matching. In order to resolve the Performance Bottleneck, we propose a simple yet quite effective method that processes the post-processing step. By rearranging the order of candidate subsequences to be compared with a query sequence, our method completely eliminates the redundancies of disk accesses and CPU processing occurring in the post-processing step. We show that our method is optimal and also does not incur any false dismissal. Also, we justify the effectiveness of our method by extensive experiments.
Sangwook Kim - One of the best experts on this subject based on the ideXlab platform.
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Performance Bottleneck of subsequence matching in time-series databases: Observation, solution, and Performance evaluation
Information Sciences, 2007Co-Authors: Sangwook Kim, Byeongsoo JeongAbstract:Abstract Subsequence matching is an operation that finds subsequences whose changing patterns are similar to a given query sequence from time-series databases. This paper identifies a Performance Bottleneck in subsequence matching, and then proposes an effective method that substantially improves the Performance of entire subsequence matching by resolving the Performance Bottleneck. First, we analyze the disk access and CPU processing times required during the index searching and post-processing steps of subsequence matching through preliminary experiments. Based on these results, we show that the post-processing step is a main Performance Bottleneck in subsequence matching. Then, we argue that the optimization of the post-processing step is a crucial issue overlooked in previous approaches. In order to resolve the Performance Bottleneck, we propose a simple yet highly effective method for expediting the post-processing step. By rearranging the order of candidate subsequences to be compared with a query sequence, our method completely eliminates the redundancies of disk accesses and CPU processing that occur in the post-processing step. Our method is fairly efficient, and does not incur any false dismissal. We quantitatively demonstrate the superiority of our method through extensive experimentation. The results show that our method produces a significantly faster post-processing step; When using a data set of real-world stock sequences, our method was 43.36–96.75 times faster than previous methods, and when using data sets of large numbers of synthetic sequences, our method was 12.48–26.95 times faster than previous methods. Also, the results show that our method reduces the weight of the post-processing step over entire subsequence matching from more than 97% to less than 67%. This implies that our method successfully resolves the Performance Bottleneck in subsequence matching. As a result, our method provides excellent Performance in entire subsequence matching. Compared with previous methods, our method is 16.17–32.64 times faster when using a data set of real-world stock sequences and 8.64–14.29 times faster when using data sets of large numbers of synthetic sequences.
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Performance Bottleneck in time series subsequence matching
ACM Symposium on Applied Computing, 2005Co-Authors: Sangwook Kim, Byeongsoo JeongAbstract:This paper addresses a Performance Bottleneck in time-series subsequence matching. First, we analyze the disk access and CPU processing times required during the index searching and post-processing steps of subsequence matching through preliminary experiments. Based on their results, we show that the post-processing step is a main Performance Bottleneck in subsequence matching. In order to resolve the Performance Bottleneck, we propose a simple yet quite effective method that processes the post-processing step. By rearranging the order of candidate subsequences to be compared with a query sequence, our method completely eliminates the redundancies of disk accesses and CPU processing occurring in the post-processing step. We show that our method is optimal and also does not incur any false dismissal. Also, we justify the effectiveness of our method by extensive experiments.
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SAC - Performance Bottleneck in time-series subsequence matching
Proceedings of the 2005 ACM symposium on Applied computing - SAC '05, 2005Co-Authors: Sangwook Kim, Byeongsoo JeongAbstract:This paper addresses a Performance Bottleneck in time-series subsequence matching. First, we analyze the disk access and CPU processing times required during the index searching and post-processing steps of subsequence matching through preliminary experiments. Based on their results, we show that the post-processing step is a main Performance Bottleneck in subsequence matching. In order to resolve the Performance Bottleneck, we propose a simple yet quite effective method that processes the post-processing step. By rearranging the order of candidate subsequences to be compared with a query sequence, our method completely eliminates the redundancies of disk accesses and CPU processing occurring in the post-processing step. We show that our method is optimal and also does not incur any false dismissal. Also, we justify the effectiveness of our method by extensive experiments.
Bin Wei - One of the best experts on this subject based on the ideXlab platform.
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Memory Performance Optimizations For Real-Time Software HDTV Decoding
Journal of VLSI signal processing systems for signal image and video technology, 2005Co-Authors: Han Chen, Bin WeiAbstract:Pure software HDTV video decoding is still a challenging task on entry-level to mid-range desktop and notebook PCs, even with today’s microprocessors frequency measured in GHz. This paper shows that the Performance Bottleneck in a software MPEG-2 decoder has been shifted to memory operations, as microprocessor technologies including multimedia instruction extensions have been improving at a fast rate during the past years. Our study exploits concurrencies at macroblock level to alleviate the Performance Bottleneck in a software MPEG-2 decoder. First, the paper introduces an interleaved block-order data layout to improve CPU cache Performance. Second, the paper describes an algorithm to explicitly prefetch macroblocks for motion compensation. Finally, the paper presents an algorithm to schedule interleaved decoding and output at macroblock level. Our implementation and experiments show that these methods can effectively hide the latency of memory and frame buffer. The optimizations improve the Performance of a multimedia-instruction-optimized software MPEG-2 decoder by a factor of about two. On a PC with a 933 MHz Pentium III CPU, the decoder can decode and display 1280 × 720-resolution HDTV streams at over 62 frames per second.
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memory Performance optimizations for real time software hdtv decoding
International Conference on Multimedia and Expo, 2002Co-Authors: Han Chen, Bin WeiAbstract:This paper shows that the Performance Bottleneck in software MPEG-2 video decoders has shifted to memory operations, as microprocessor technologies have been improving at a fast rate during the past few years. We exploit concurrencies between the processor and the memory sub-system at macroblock level to alleviate the Performance Bottleneck. First, the paper introduces an interleaved-block order data layout to improve cache Performance. Second, the paper describes an algorithm to explicitly prefetch macroblocks for motion compensation. Finally, the paper presents an algorithm to schedule interleaved decoding and output at macroblock level. Our implementation and experiments show that these methods successfully hide the latency of memory and frame buffer. These techniques improve the Performance of an already optimized software MPEG-2 decoder by about a factor of two. On a 933 MHz Pentium III PC, the decoder can play 720p HDTV streams at over 62 frames per second.
Badrinath K. Sridharan - One of the best experts on this subject based on the ideXlab platform.
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guarding fast data delivery in cloud an effective approach to isolating Performance Bottleneck during slow data delivery
International Conference on Cloud Computing, 2015Co-Authors: Zhenyun Zhuang, Haricharan Ramachandra, Badrinath K. SridharanAbstract:Cloud-based products heavily rely on the fast data delivery between data centers and remote users - when data delivery is slow, the products' Performance is crippled. When slow data delivery occurs, engineers need to investigate and root cause the issue. To facilitate the investigations, we propose an algorithm to automatically identify the Performance Bottleneck. The algorithm aggregates information from multiple layers of data sender and receiver. It helps to automatically isolate the problem type by identifying which component of sender/receiver/network is the Bottleneck. After isolation, successive efforts can be taken to root cause the exact problem. We also build a prototype to demonstrate the effectiveness of the algorithm.
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CloudCom-Asia - Guarding Fast Data Delivery in Cloud: An Effective Approach to Isolating Performance Bottleneck During Slow Data Delivery
Cloud Computing and Big Data, 2015Co-Authors: Zhenyun Zhuang, Haricharan Ramachandra, Badrinath K. SridharanAbstract:Cloud-based products heavily rely on the fast data delivery between data centers and remote users - when data delivery is slow, the products' Performance is crippled. When slow data delivery occurs, engineers need to investigate and root cause the issue. To facilitate the investigations, we propose an algorithm to automatically identify the Performance Bottleneck. The algorithm aggregates information from multiple layers of data sender and receiver. It helps to automatically isolate the problem type by identifying which component of sender/receiver/network is the Bottleneck. After isolation, successive efforts can be taken to root cause the exact problem. We also build a prototype to demonstrate the effectiveness of the algorithm.
Han Chen - One of the best experts on this subject based on the ideXlab platform.
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Memory Performance Optimizations For Real-Time Software HDTV Decoding
Journal of VLSI signal processing systems for signal image and video technology, 2005Co-Authors: Han Chen, Bin WeiAbstract:Pure software HDTV video decoding is still a challenging task on entry-level to mid-range desktop and notebook PCs, even with today’s microprocessors frequency measured in GHz. This paper shows that the Performance Bottleneck in a software MPEG-2 decoder has been shifted to memory operations, as microprocessor technologies including multimedia instruction extensions have been improving at a fast rate during the past years. Our study exploits concurrencies at macroblock level to alleviate the Performance Bottleneck in a software MPEG-2 decoder. First, the paper introduces an interleaved block-order data layout to improve CPU cache Performance. Second, the paper describes an algorithm to explicitly prefetch macroblocks for motion compensation. Finally, the paper presents an algorithm to schedule interleaved decoding and output at macroblock level. Our implementation and experiments show that these methods can effectively hide the latency of memory and frame buffer. The optimizations improve the Performance of a multimedia-instruction-optimized software MPEG-2 decoder by a factor of about two. On a PC with a 933 MHz Pentium III CPU, the decoder can decode and display 1280 × 720-resolution HDTV streams at over 62 frames per second.
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memory Performance optimizations for real time software hdtv decoding
International Conference on Multimedia and Expo, 2002Co-Authors: Han Chen, Bin WeiAbstract:This paper shows that the Performance Bottleneck in software MPEG-2 video decoders has shifted to memory operations, as microprocessor technologies have been improving at a fast rate during the past few years. We exploit concurrencies between the processor and the memory sub-system at macroblock level to alleviate the Performance Bottleneck. First, the paper introduces an interleaved-block order data layout to improve cache Performance. Second, the paper describes an algorithm to explicitly prefetch macroblocks for motion compensation. Finally, the paper presents an algorithm to schedule interleaved decoding and output at macroblock level. Our implementation and experiments show that these methods successfully hide the latency of memory and frame buffer. These techniques improve the Performance of an already optimized software MPEG-2 decoder by about a factor of two. On a 933 MHz Pentium III PC, the decoder can play 720p HDTV streams at over 62 frames per second.
