The Experts below are selected from a list of 135 Experts worldwide ranked by ideXlab platform

Sudhakar Yalamanchili - One of the best experts on this subject based on the ideXlab platform.

  • ICPP, Vol. 1 - A high Performance Router architecture for interconnection networks
    Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing, 1996
    Co-Authors: José Duato, Pedro Garcia Lopez, Federico Silla, Sudhakar Yalamanchili
    Abstract:

    We propose a new Router architecture that supports wormhole switching and circuit switching concurrently. This architecture has been designed to take advantage of temporal communication locality. This can be done by establishing a circuit between nodes that are going to communicate frequently. Messages using those circuits face no contention. By combining circuit switching, pre-established physical circuits and wave pipelining across channels and switches, it is possible to increase network bandwidth considerably, also reducing latency for communications that use pre-established physical circuits. This Router architecture also allows to reduce the overhead of the software messaging layer in multicomputers by offering a better hardware support. Preliminary Performance evaluation results show a drastic reduction in latency and increment in throughput when messages are long enough, even if circuits are established for a single transmission and locality is not exploited.

  • a high Performance Router architecture for interconnection networks
    International Conference on Parallel Processing, 1996
    Co-Authors: José Duato, Federico Silla, Pedro Lopez, Sudhakar Yalamanchili
    Abstract:

    We propose a new Router architecture that supports wormhole switching and circuit switching concurrently. This architecture has been designed to take advantage of temporal communication locality. This can be done by establishing a circuit between nodes that are going to communicate frequently. Messages using those circuits face no contention. By combining circuit switching, pre-established physical circuits and wave pipelining across channels and switches, it is possible to increase network bandwidth considerably, also reducing latency for communications that use pre-established physical circuits. This Router architecture also allows to reduce the overhead of the software messaging layer in multicomputers by offering a better hardware support. Preliminary Performance evaluation results show a drastic reduction in latency and increment in throughput when messages are long enough, even if circuits are established for a single transmission and locality is not exploited.

D. S. Wills - One of the best experts on this subject based on the ideXlab platform.

  • HiPER-P : An efficient, High-Performance Router for multicomputer interconnection networks
    Lecture Notes in Computer Science, 1998
    Co-Authors: P. May, S. M. Chai, D. S. Wills
    Abstract:

    As high Performance parallel computing architectures make their way into systems with tight size, weight, power, and energy budgets (e.g., portable computing and communications, autonomous vehicles, and space-borne computing), compact and efficient computing and communication mechanisms will be required. To provide such a communication mechanism, the Portable Image Computing Architectures (PICA) group at Georgia Tech is designing the High-Performance Efficient Router (HiPER), a multidimensional Router with high-throughput serial channels (1-2 Gbps). Providing high Performance for size, weight, power, and energy constrained systems requires careful attention to routing, switching, and error control mechanisms, and the HiPER Prototype (HiPER-P) is a proof-of-concept vehicle that will validate efficient implementations of these mechanisms. The HiPER-P combines mad postman (bit-pipelined) switching with dimension-order routing, producing a Router with a very low-latency routing function. To maintain robust communication as link speeds increase and link power budgets decrease, the HiPER-P provides flit-level hop-by-hop retransmission of erroneous flits. This error control mechanism provides built-in error control at the network level. The design of the HiPER-P is presented in this paper as well as results of Performance simulations which characterize mad postman switching combined with flit-level error control.

  • PCRCW - HiPER-P: An Efficient, High-Performance Router for Multicomputer Interconnection Networks
    Parallel Computer Routing and Communication, 1998
    Co-Authors: P. May, S. M. Chai, D. S. Wills
    Abstract:

    As high Performance parallel computing architectures make their way into systems with tight size, weight, power, and energy budgets (e.g., portable computing and communications, autonomous vehicles, and space-borne computing), compact and efficient computing and communication mechanisms will be required. To provide such a communication mechanism, the Portable Image Computing Architectures (PICA) group at Georgia Tech is designing the High-Performance Efficient Router (HiPER), a multidimensional Router with high-throughput serial channels (1-2 Gbps). Providing high Performance for size, weight, power, and energy constrained systems requires careful attention to routing, switching, and error control mechanisms, and the HiPER Prototype (HiPER-P) is a proof-of-concept vehicle that will validate efficient implementations of these mechanisms. The HiPER-P combines mad postman (bit- pipelined) switching with dimension-order routing, producing a Router with a very low-latency routing function. To maintain robust communication as link speeds increase and link power budgets decrease, the HiPER-P provides flit-level hop-by-hop retransmission of erroneous flits. This error control mechanism provides built-in error control at the network level. The design of the HiPER-P is presented in this paper as well as results of Performance simulations which characterize mad postman switching combined with flit-level error control.

José Duato - One of the best experts on this subject based on the ideXlab platform.

  • ICPP, Vol. 1 - A high Performance Router architecture for interconnection networks
    Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing, 1996
    Co-Authors: José Duato, Pedro Garcia Lopez, Federico Silla, Sudhakar Yalamanchili
    Abstract:

    We propose a new Router architecture that supports wormhole switching and circuit switching concurrently. This architecture has been designed to take advantage of temporal communication locality. This can be done by establishing a circuit between nodes that are going to communicate frequently. Messages using those circuits face no contention. By combining circuit switching, pre-established physical circuits and wave pipelining across channels and switches, it is possible to increase network bandwidth considerably, also reducing latency for communications that use pre-established physical circuits. This Router architecture also allows to reduce the overhead of the software messaging layer in multicomputers by offering a better hardware support. Preliminary Performance evaluation results show a drastic reduction in latency and increment in throughput when messages are long enough, even if circuits are established for a single transmission and locality is not exploited.

  • a high Performance Router architecture for interconnection networks
    International Conference on Parallel Processing, 1996
    Co-Authors: José Duato, Federico Silla, Pedro Lopez, Sudhakar Yalamanchili
    Abstract:

    We propose a new Router architecture that supports wormhole switching and circuit switching concurrently. This architecture has been designed to take advantage of temporal communication locality. This can be done by establishing a circuit between nodes that are going to communicate frequently. Messages using those circuits face no contention. By combining circuit switching, pre-established physical circuits and wave pipelining across channels and switches, it is possible to increase network bandwidth considerably, also reducing latency for communications that use pre-established physical circuits. This Router architecture also allows to reduce the overhead of the software messaging layer in multicomputers by offering a better hardware support. Preliminary Performance evaluation results show a drastic reduction in latency and increment in throughput when messages are long enough, even if circuits are established for a single transmission and locality is not exploited.

  • A high Performance Router architecture for multimedia applications
    Proceedings. Fifth International Conference on Massively Parallel Processing (Cat. No.98EX182), 1
    Co-Authors: Juan M. Orduña, José Duato
    Abstract:

    Parallel computing systems and network of workstations (NOW) are being used nowadays for on-line multimedia applications. The potential market of such applications seems to be large enough to justify a specific architecture oriented to support them more efficiently. Wave switching is a hybrid switching technique for high Performance Routers that combines wormhole switching and circuit switching in the same Router architecture. This switching technique is very well suited for parallel computers and NOWs using optical interconnections. In this paper we propose the use of wave switching for applications like distributed multimedia systems or MPEG video encoding. These applications generate an intensive, bursty traffic together with a small percentage of control message traffic. For this kind of traffic, wave switching can considerably improve the throughput of parallel computing systems. Performance evaluation results for a MPEG video encoding application show a drastic reduction in latency and an improvement in throughput, making easier for these systems to support real-time constraints.

P. May - One of the best experts on this subject based on the ideXlab platform.

  • HiPER-P : An efficient, High-Performance Router for multicomputer interconnection networks
    Lecture Notes in Computer Science, 1998
    Co-Authors: P. May, S. M. Chai, D. S. Wills
    Abstract:

    As high Performance parallel computing architectures make their way into systems with tight size, weight, power, and energy budgets (e.g., portable computing and communications, autonomous vehicles, and space-borne computing), compact and efficient computing and communication mechanisms will be required. To provide such a communication mechanism, the Portable Image Computing Architectures (PICA) group at Georgia Tech is designing the High-Performance Efficient Router (HiPER), a multidimensional Router with high-throughput serial channels (1-2 Gbps). Providing high Performance for size, weight, power, and energy constrained systems requires careful attention to routing, switching, and error control mechanisms, and the HiPER Prototype (HiPER-P) is a proof-of-concept vehicle that will validate efficient implementations of these mechanisms. The HiPER-P combines mad postman (bit-pipelined) switching with dimension-order routing, producing a Router with a very low-latency routing function. To maintain robust communication as link speeds increase and link power budgets decrease, the HiPER-P provides flit-level hop-by-hop retransmission of erroneous flits. This error control mechanism provides built-in error control at the network level. The design of the HiPER-P is presented in this paper as well as results of Performance simulations which characterize mad postman switching combined with flit-level error control.

  • PCRCW - HiPER-P: An Efficient, High-Performance Router for Multicomputer Interconnection Networks
    Parallel Computer Routing and Communication, 1998
    Co-Authors: P. May, S. M. Chai, D. S. Wills
    Abstract:

    As high Performance parallel computing architectures make their way into systems with tight size, weight, power, and energy budgets (e.g., portable computing and communications, autonomous vehicles, and space-borne computing), compact and efficient computing and communication mechanisms will be required. To provide such a communication mechanism, the Portable Image Computing Architectures (PICA) group at Georgia Tech is designing the High-Performance Efficient Router (HiPER), a multidimensional Router with high-throughput serial channels (1-2 Gbps). Providing high Performance for size, weight, power, and energy constrained systems requires careful attention to routing, switching, and error control mechanisms, and the HiPER Prototype (HiPER-P) is a proof-of-concept vehicle that will validate efficient implementations of these mechanisms. The HiPER-P combines mad postman (bit- pipelined) switching with dimension-order routing, producing a Router with a very low-latency routing function. To maintain robust communication as link speeds increase and link power budgets decrease, the HiPER-P provides flit-level hop-by-hop retransmission of erroneous flits. This error control mechanism provides built-in error control at the network level. The design of the HiPER-P is presented in this paper as well as results of Performance simulations which characterize mad postman switching combined with flit-level error control.

Zhang Hui - One of the best experts on this subject based on the ideXlab platform.

  • Method of Buffersize Computation Based on Fractional Alpha Traffic Model
    Computer Engineering, 2007
    Co-Authors: Zhang Hui
    Abstract:

    The buffersize is an essential part of a high Performance Router design. The common method of buffersize computation is based on Poisson traffic model. This method is not in conformity to the actual traffic characteristic and it will cause high rate of packet loss. The proposed fractional Alpha traffic model can denote the characteristic of self-similar and non-Gaussian. The residual distribution function (RDF) based on the fractional Alpha model fit the real traffic better than the RDF based on other models. Based on the new RDF, a method for computing the buffersize is got and used in the high Performance Router design. The method is simple and the result is satisfying.