The Experts below are selected from a list of 144 Experts worldwide ranked by ideXlab platform
Jorg Henkel - One of the best experts on this subject based on the ideXlab platform.
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raise reliability aware instruction scheduling for unreliable hardware
Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (Pipeline, Register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the Pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
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ASP-DAC - RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware
17th Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (Pipeline, Register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the Pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
Semeen Rehman - One of the best experts on this subject based on the ideXlab platform.
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raise reliability aware instruction scheduling for unreliable hardware
Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (Pipeline, Register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the Pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
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ASP-DAC - RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware
17th Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (Pipeline, Register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the Pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
Florian Kriebel - One of the best experts on this subject based on the ideXlab platform.
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raise reliability aware instruction scheduling for unreliable hardware
Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (Pipeline, Register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the Pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
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ASP-DAC - RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware
17th Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (Pipeline, Register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the Pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
Muhammad Shafique - One of the best experts on this subject based on the ideXlab platform.
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raise reliability aware instruction scheduling for unreliable hardware
Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (Pipeline, Register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the Pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
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ASP-DAC - RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware
17th Asia and South Pacific Design Automation Conference, 2012Co-Authors: Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jorg HenkelAbstract:A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (Pipeline, Register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the Pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.
Vasile Gheorghita Gaitan - One of the best experts on this subject based on the ideXlab platform.
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An Approach of nMPRA Architecture using Hardware Implemented Support for Event Prioritization and Treating
International Journal of Advanced Computer Science and Applications, 2017Co-Authors: Ionel Zagan, Nicoleta Cristina Gaitan, Vasile Gheorghita GaitanAbstract:One of the fundamental requirements of real time operating systems is the determinism of executing critical tasks and treating multiple periodic or aperiodic events. The present paper presents the hardware support of the nMPRA processor (Multi Pipeline Register Architecture) dedicated to treating time events, interrupt events and events associated with synchronization and inter-task communication mechanisms. Because in real time systems the treatment of events is a very important aspect, this paper describes both the mechanism implemented in hardware for prioritizing and treating multiple events, and the experimental results obtained using Virtex-7 FPGA circuit. The article's element of originality is the very short response time required in treating and prioritizing events.
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Schedulability analysis of nMPRA processor based on multithreaded execution
2016 International Conference on Development and Application Systems (DAS), 2016Co-Authors: Ionel Zagan, Vasile Gheorghita GaitanAbstract:This article presents several solutions meant to improve the performance of CPU architecture and it describes a fine-grained multithreading architecture empowered with a hardware scheduler that uses remapping techniques for the program counter, the Register file and the Pipeline Registers. In this context, our main contribution relates to a custom CPU implementation in order to provide predictability execution for hard real-time tasks. Experimental data obtained during tests is analyzed in order to validate the proposed CPU, based on a fine-grained multithreading architecture and a fast switching operation between a blocked task and another one, scheduled by Hardware Scheduler Engine (nHSE). The resource differences between the original Multi Pipeline Register Architecture (nMPRA) implementation and the multithreading configuration are also taken in consideration.
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Improving interrupt handling in the nMPRA
2014 International Conference on Development and Application Systems (DAS), 2014Co-Authors: Nicoleta Cristina Gaitan, Vasile Gheorghita Gaitan, Elena-eugenia Ciobanu MoisucAbstract:In the most Real Time Operating Systems (RTOS), the interrupt handlers are implemented in software and they can increase the response time to external events and the overload of the CPU. Therefore, the newest RTOSs implement in hardware the interrupt handlers in order to eliminate these two problems. By analyzing traditional models for the management of interrupts, we can emphasize their inability to provide the temporal determinism required in real-time systems. This paper presents an interrupt handler implemented in hardware based on a method that uses a unified space of priorities for the tasks and interrupts, so there is not a specialized interrupt controller. This solution is integrated in the MPRA (Multi Pipeline Register Architecture) processor that contains a hardware RTOS. The major difference compared to other architectures with hardware scheduler is that the MPRA is a multi-Pipeline architecture, which means that each task has its own set of Pipeline Registers.
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custom designed cpu architecture based on a hardware scheduler and independent Pipeline Registers concept and theory of operation
Electro Information Technology, 2012Co-Authors: Eugen Dodiu, Vasile Gheorghita GaitanAbstract:System response time is a key element in hard real time systems. In classical Real Time Operating Systems (RTOS) based on software schedulers, overhead and jitter are a major problem when the number of tasks and the rate of context switches are high. Increased values for those parameters over admissible values can lead to performance degradation, increased power consumption or even deadline misses. If a part of the scheduling components or the entire functionality is moved from software to hardware, a significant improvement in task switching times can be achieved. This paper presents a custom designed multi Pipeline Register architecture (MPRA) that has a dedicated hardware scheduler unit integrated into the CPU.
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EIT - Custom designed CPU architecture based on a hardware scheduler and independent Pipeline Registers — Concept and theory of operation
2012 IEEE International Conference on Electro Information Technology, 2012Co-Authors: Eugen Dodiu, Vasile Gheorghita GaitanAbstract:System response time is a key element in hard real time systems. In classical Real Time Operating Systems (RTOS) based on software schedulers, overhead and jitter are a major problem when the number of tasks and the rate of context switches are high. Increased values for those parameters over admissible values can lead to performance degradation, increased power consumption or even deadline misses. If a part of the scheduling components or the entire functionality is moved from software to hardware, a significant improvement in task switching times can be achieved. This paper presents a custom designed multi Pipeline Register architecture (MPRA) that has a dedicated hardware scheduler unit integrated into the CPU.