The Experts below are selected from a list of 36873 Experts worldwide ranked by ideXlab platform
Bertan Bakkaloglu - One of the best experts on this subject based on the ideXlab platform.
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a 6 a 93 peak efficiency 4 phase digitally synchronized hysteretic buck Converter with 1 5 frequency and 3 6 current sharing error
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc–dc Converter achieves 93% peak efficiency for $V_{i}= 2$ V and $V_{o}= 1.6$ V.
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A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc-dc Converter achieves 93% peak efficiency for Vi = 2 V and Vo = 1.6 V.
Zhe Yang - One of the best experts on this subject based on the ideXlab platform.
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a 6 a 93 peak efficiency 4 phase digitally synchronized hysteretic buck Converter with 1 5 frequency and 3 6 current sharing error
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc–dc Converter achieves 93% peak efficiency for $V_{i}= 2$ V and $V_{o}= 1.6$ V.
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A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc-dc Converter achieves 93% peak efficiency for Vi = 2 V and Vo = 1.6 V.
P C Adell - One of the best experts on this subject based on the ideXlab platform.
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a 6 a 93 peak efficiency 4 phase digitally synchronized hysteretic buck Converter with 1 5 frequency and 3 6 current sharing error
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc–dc Converter achieves 93% peak efficiency for $V_{i}= 2$ V and $V_{o}= 1.6$ V.
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A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc-dc Converter achieves 93% peak efficiency for Vi = 2 V and Vo = 1.6 V.
Debashis Mandal - One of the best experts on this subject based on the ideXlab platform.
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a 6 a 93 peak efficiency 4 phase digitally synchronized hysteretic buck Converter with 1 5 frequency and 3 6 current sharing error
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc–dc Converter achieves 93% peak efficiency for $V_{i}= 2$ V and $V_{o}= 1.6$ V.
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A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc-dc Converter achieves 93% peak efficiency for Vi = 2 V and Vo = 1.6 V.
Kishan Joshi - One of the best experts on this subject based on the ideXlab platform.
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a 6 a 93 peak efficiency 4 phase digitally synchronized hysteretic buck Converter with 1 5 frequency and 3 6 current sharing error
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc–dc Converter achieves 93% peak efficiency for $V_{i}= 2$ V and $V_{o}= 1.6$ V.
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A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Zhe Yang, Kishan Joshi, Debashis Mandal, P C Adell, Bertan BakkalogluAbstract:A four-phase, quasi-current-mode hysteretic buck Converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic Converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3-9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual Converter phases can be disabled, and the final stage Power Converter Output stage is segmented for high efficiency. The dc-dc Converter achieves 93% peak efficiency for Vi = 2 V and Vo = 1.6 V.