The Experts below are selected from a list of 3225 Experts worldwide ranked by ideXlab platform
Viktor K Prasanna - One of the best experts on this subject based on the ideXlab platform.
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ASAP - Large-scale packet classification on FPGA
2015 IEEE 26th International Conference on Application-specific Systems Architectures and Processors (ASAP), 2015Co-Authors: Shijie Zhou, Yun R. Qu, Viktor K PrasannaAbstract:Packet classification is a key network function enabling a variety of network applications, such as network security, Quality of Service (QoS) routing, and other value-added services. Routers perform packet classification based on a Predefined Rule set. Packet classification faces two challenges: (1) the data rate of the network traffic keeps increasing, and (2) the size of the Rule sets are becoming very large. In this paper, we propose an FPGA-based packet classification engine for large Rule sets. We present a decomposition-based approach, where each field of the packet header is searched separately. Then we merge the partial search results from all the fields using a merging network. Experimental results show that our design can achieve a throughput of 147 Million Packets Per Second (MPPS), while supporting upto 256K Rules on a state-of-the-art FPGA. Compared to the prior works on FPGA or multi-core processors, our design demonstrates significant performance improvements.
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stridebv single chip 400g packet classification
High Performance Switching and Routing, 2012Co-Authors: Thilan Ganegedara, Viktor K PrasannaAbstract:Hardware firewalls act as the first line of defense in protecting networks against attacks. Packets are organized into flows based on a set of packet header fields and a Predefined Rule is applied on the packets in each flow to filter malicious network traffic. This is realized using packet classification, which is implemented in secure networking environments where mere best-effort delivery of packets is not adequate. Existing packet classification solutions are highly dependent on the properties (or features) of the Ruleset. We present a bit vector based lookup scheme and a parallel hardware architecture that does not rely on Ruleset features. A detailed performance analysis of the proposed scheme is given under different configurations. Post place-and-route results of our parallel pipelined architecture on a state-of-the-art Field Programmable Gate Array (FPGA) device shows that for real-life firewall Rulesets, the proposed solution achieves 400G+ throughput. To the best of our knowledge, this is the first packet classification engine that achieves 400G+ rate on a single FPGA. Further, on the average we achieve 2.5× power efficiency compared with the state-of-the-art solutions.
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HPSR - StrideBV: Single chip 400G+ packet classification
2012 IEEE 13th International Conference on High Performance Switching and Routing, 2012Co-Authors: Thilan Ganegedara, Viktor K PrasannaAbstract:Hardware firewalls act as the first line of defense in protecting networks against attacks. Packets are organized into flows based on a set of packet header fields and a Predefined Rule is applied on the packets in each flow to filter malicious network traffic. This is realized using packet classification, which is implemented in secure networking environments where mere best-effort delivery of packets is not adequate. Existing packet classification solutions are highly dependent on the properties (or features) of the Ruleset. We present a bit vector based lookup scheme and a parallel hardware architecture that does not rely on Ruleset features. A detailed performance analysis of the proposed scheme is given under different configurations. Post place-and-route results of our parallel pipelined architecture on a state-of-the-art Field Programmable Gate Array (FPGA) device shows that for real-life firewall Rulesets, the proposed solution achieves 400G+ throughput. To the best of our knowledge, this is the first packet classification engine that achieves 400G+ rate on a single FPGA. Further, on the average we achieve 2.5× power efficiency compared with the state-of-the-art solutions.
Nick Mckeown - One of the best experts on this subject based on the ideXlab platform.
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algorithms for packet classification
IEEE Network, 2001Co-Authors: Pankaj Gupta, Nick MckeownAbstract:The process of categorizing packets into "flows" in an Internet router is called packet classification. All packets belonging to the same flow obey a Predefined Rule and are processed in a similar manner by the router. For example, all packets with the same source and destination IP addresses may be defined to form a flow. Packet classification is needed for non-best-effort services, such as firewalls and quality of service; services that require the capability to distinguish and isolate traffic in different flows for suitable processing. In general, packet classification on multiple fields is a difficult problem. Hence, researchers have proposed a variety of algorithms which, broadly speaking, can be categorized as basic search algorithms, geometric algorithms, heuristic algorithms, or hardware-specific search algorithms. In this tutorial we describe algorithms that are representative of each category, and discuss which type of algorithm might be suitable for different applications.
Sedef Kent - One of the best experts on this subject based on the ideXlab platform.
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Edge detection in remote sensing images via lattice filters based subband decomposition
2009 4th International Conference on Recent Advances in Space Technologies, 2009Co-Authors: Nur Huseyin Kaplan, Isin Erer, Sedef KentAbstract:A new edge detection algorithm based on the subband decomposition using lattice filter structures is presented. The method is used for the edge detection of remote sensing images. The image is decomposed into subband images using 1-D lattice filters, these sub-images are combined in the subband domain using a Predefined Rule and edges of the image are detected.
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Fusion Of Remote Sensing Images via Lattice Filters
2007 3rd International Conference on Recent Advances in Space Technologies, 2007Co-Authors: Nur Huseyin Kaplan, Isin Erer, Sedef KentAbstract:A new image fusion algorithm based on the subband decomposition of the source images using 2-D separable lattice filters is presented. The method is used for the fusion of multispectral and SAR data. The source images are decomposed into subband images using separable lattice filters, these images are combined in the subband domain using a Predefined Rule, then the fused image is obtained by the inverse lattice filter.
Thilan Ganegedara - One of the best experts on this subject based on the ideXlab platform.
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stridebv single chip 400g packet classification
High Performance Switching and Routing, 2012Co-Authors: Thilan Ganegedara, Viktor K PrasannaAbstract:Hardware firewalls act as the first line of defense in protecting networks against attacks. Packets are organized into flows based on a set of packet header fields and a Predefined Rule is applied on the packets in each flow to filter malicious network traffic. This is realized using packet classification, which is implemented in secure networking environments where mere best-effort delivery of packets is not adequate. Existing packet classification solutions are highly dependent on the properties (or features) of the Ruleset. We present a bit vector based lookup scheme and a parallel hardware architecture that does not rely on Ruleset features. A detailed performance analysis of the proposed scheme is given under different configurations. Post place-and-route results of our parallel pipelined architecture on a state-of-the-art Field Programmable Gate Array (FPGA) device shows that for real-life firewall Rulesets, the proposed solution achieves 400G+ throughput. To the best of our knowledge, this is the first packet classification engine that achieves 400G+ rate on a single FPGA. Further, on the average we achieve 2.5× power efficiency compared with the state-of-the-art solutions.
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HPSR - StrideBV: Single chip 400G+ packet classification
2012 IEEE 13th International Conference on High Performance Switching and Routing, 2012Co-Authors: Thilan Ganegedara, Viktor K PrasannaAbstract:Hardware firewalls act as the first line of defense in protecting networks against attacks. Packets are organized into flows based on a set of packet header fields and a Predefined Rule is applied on the packets in each flow to filter malicious network traffic. This is realized using packet classification, which is implemented in secure networking environments where mere best-effort delivery of packets is not adequate. Existing packet classification solutions are highly dependent on the properties (or features) of the Ruleset. We present a bit vector based lookup scheme and a parallel hardware architecture that does not rely on Ruleset features. A detailed performance analysis of the proposed scheme is given under different configurations. Post place-and-route results of our parallel pipelined architecture on a state-of-the-art Field Programmable Gate Array (FPGA) device shows that for real-life firewall Rulesets, the proposed solution achieves 400G+ throughput. To the best of our knowledge, this is the first packet classification engine that achieves 400G+ rate on a single FPGA. Further, on the average we achieve 2.5× power efficiency compared with the state-of-the-art solutions.
Pankaj Gupta - One of the best experts on this subject based on the ideXlab platform.
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algorithms for packet classification
IEEE Network, 2001Co-Authors: Pankaj Gupta, Nick MckeownAbstract:The process of categorizing packets into "flows" in an Internet router is called packet classification. All packets belonging to the same flow obey a Predefined Rule and are processed in a similar manner by the router. For example, all packets with the same source and destination IP addresses may be defined to form a flow. Packet classification is needed for non-best-effort services, such as firewalls and quality of service; services that require the capability to distinguish and isolate traffic in different flows for suitable processing. In general, packet classification on multiple fields is a difficult problem. Hence, researchers have proposed a variety of algorithms which, broadly speaking, can be categorized as basic search algorithms, geometric algorithms, heuristic algorithms, or hardware-specific search algorithms. In this tutorial we describe algorithms that are representative of each category, and discuss which type of algorithm might be suitable for different applications.
