The Experts below are selected from a list of 11700 Experts worldwide ranked by ideXlab platform
Suryadinata Adrian - One of the best experts on this subject based on the ideXlab platform.
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Implementasi Audio Equalizer Digital Grafis dengan Digital Signal Processor Board OMAP-L137
2017Co-Authors: Pranjoto Hartono, Lestariningsih Diana, Suryadinata AdrianAbstract:A digital audio equalizer is implemented using a Digital Signal Processor Board OMAP-L137 with display using a computer monitor with digital control. Traditional audio equalizer with sliding buttons is replaced with a display on a computer screen that is similar to a traditional equalizer-look. The equalizer designed here is a 2/3 octave audio equalizer with left and right audio channel designed in accordance with the standards set forth in ISO 266 1997, IEC 1995 and ISO 61260/1260 3 1973. The standards also mentioned wide band every frequency channels with a bandwidth of bandpass filter with a -3dB at strengthening maximum / minimum +/- 6dB on any frequency channel (left-right independent). The equalizer main component is bandpass filter with a center-predetermined frequency based on standards for the bandwidth of which have been determined in accordance with ISO 266 and so on as mentioned above. Determination is to use the ribbon width of -3dB attenuation on both sides of the bandpass filter, which was also mentioned in the standard. Implementation bandpass filter is to use a Butterworth filter of order 1. The transformation from Butterworth 1st order low pass filter 1 (analog) into a first order bandpass filter (digital) is bilinear Z-transform. Implementation of the digital filter is a signal Processor from Texas Instruments with SDK module OMAP-L137 Processor from Texas Instruments which is able to perform calculations quickly to a digital signal processing system. Every computed bandpass filter will be evaluated fir is amplitude, phase response and bandwidth. The result of the computation for each bandpass filter in general and final implementation will be presented. The performance of OMAP-L137 to handle all the filters without any problems will be presente
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IMPLEMENTASI AUDIO EQUALIZER DIGITAL GRAFIS DENGAN DIGITAL SIGNAL Processor Board OMAP-L137
Program Studi Teknik Elektro, 2016Co-Authors: Pranjoto Hartono, Lestariningsih Diana, Suryadinata AdrianAbstract:Sebuah equalizer audio digital dibuat dengan menggunakan Digital Signal Processor Board OMAP-L137 dan tampilan tombol dirancang secara digital dengan menggunakan komputer. Equalizer audio grafis (audio graphic equalizer) tradisional dengan tombol geser (slider button) akan digantikan dengan sebuah tampilan pada layar komputer yang mirip dengan tampilan tradisional. Equalizer dibuat dengan menggunakan pemisahan kanal audio 2/3 oktaf untuk jalur kiri dan jalur kanan dirancang sesuai dengan standar baku yang dituangkan dalam ISO 266 tahun 1997, IEC 61260/1260 tahun 1995 dan ISO 3 tahun 1973. Pada standar tersebut juga disebutkan lebar pita setiap kanal frekuensi dengan bandwidth -3dB pada bandpass filter dengan penguatan maximum/ minimum +/-6dB pada setiap kanal frekuensi (kiri-kanan independen).Komponen utama equliazer adalah bandpass filter dengan center-frequency yang telah ditentukan berdasarkan standar yang berlaku dengan lebar pita (bandwidth) sebesar yang telah ditentukan sesuai dengan ISO 266 tahun 1997 seperti yang telah disebutkan di atas. Penentuan lebar pita adalah dengan menggunakan attenuasi sebesar -3dB pada kedua sisi dari bandpass filter tersebut yang juga disebutkan dalam standar. Implementasi bandpass filter adalah dengan menggunakan filter Butterworth orde 1 dan pengubah dari lowpass filter Butterworth orde 1 (analog) menjadi bandpass filter orde 1 (digital) menggunakan metode Bilinear Z-transform.Implementasi dari filter digital tersebut adalah sebuah prosesor sinyal dari Texas Instruments dengan modul SDK OMAP-L137 dari Texas Instruments dimana prosesor tersebut mampu melakukan penghitungan secara cepat untuk sebuah sistem pemrosesan sinyal digital. Hasil penghitungan untuk setiap filter dan juga hasil akhir dari implementasi filter ini akan dipaparkan. Kata kunci: digital equalizer 2/3 oktaf, digital signal processing, OMAP-L137, TMS320C674x
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Implementasi Audio Equalizer Digital Grafis Dengan Digital Signal Processor Board Omap-L137
Unika Atama Jaya, 2016Co-Authors: Pranjoto Hartono, Lestariningsih Diana, Suryadinata AdrianAbstract:Sebuah equalizer audio digital dibuat dengan menggunakan Digital Signal Processor Board OMAP-L137 dan tampilan tombol dirancang secara digital dengan menggunakan komputer. Equalizer audio grafis (audio graphic equalizer) tradisional dengan tombol geser (slider button) akan digantikan dengan sebuah tampilan pada layar komputer yang mirip dengan tampilan tradisional. Equalizer dibuat dengan menggunakan pemisahan kanal audio 2/3 oktaf untuk jalur kiri dan jalur kanan dirancang sesuai dengan standar baku yang dituangkan dalam ISO 266 tahun 1997, IEC 61260/1260 tahun 1995 dan ISO 3 tahun 1973. Pada standar tersebut juga disebutkan lebar pita setiap kanal frekuensi dengan bandwidth -3dB pada bandpass filter dengan penguatan maximum/ minimum +/-6dB pada setiap kanal frekuensi (kiri-kanan independen). Komponen utama equliazer adalah bandpass filter dengan center-frequency yang telah ditentukan berdasarkan standar yang berlaku dengan lebar pita (bandwidth) sebesar yang telah ditentukan sesuai dengan ISO 266 tahun 1997 seperti yang telah disebutkan di atas. Penentuan lebar pita adalah dengan menggunakan attenuasi sebesar -3dB pada kedua sisi dari bandpass filter tersebut yang juga disebutkan dalam standar. Implementasi bandpass filter adalah dengan menggunakan filter Butterworth orde 1 dan pengubah dari lowpass filter Butterworth orde 1 (analog) menjadi bandpass filter orde 1 (digital) menggunakan metode Bilinear Z-transform. Implementasi dari filter digital tersebut adalah sebuah prosesor sinyal dari Texas Instruments dengan modul SDK OMAP-L137 dari Texas Instruments dimana prosesor tersebut mampu melakukan penghitungan secara cepat untuk sebuah sistem pemrosesan sinyal digital. Hasil penghitungan untuk setiap filter dan juga hasil akhir dari implementasi filter ini akan dipaparkan
M N Uddin - One of the best experts on this subject based on the ideXlab platform.
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an adaptive filter based torque ripple minimization of a fuzzy logic controller for speed control of ipm motor drives
IEEE Transactions on Industry Applications, 2011Co-Authors: M N UddinAbstract:This paper presents an adaptive-filter-based torque-ripple minimization (TRM) of a fuzzy-logic controller (FLC) for speed control of an interior permanent magnet (IPM) motor drive. A simple and effective first-order digital infinite impulse response filter is utilized to reduce the torque ripples introduced by the FLC. The gain of the filter is adapted online based on the magnitude of the torque ripple. The optimal position of the filter in the complete drive is also determined for effective TRM. The various sources of torque pulsations in a practical electric-machine drive are described. The main causes of the torque ripple in an FLC are also explained. A simulation model for closed vector control of an FLC-based IPM motor drive incorporating the proposed TRM technique is developed in Matlab/Simulink. The complete drive is also experimentally implemented using digital signal Processor Board DS1102 for a laboratory 1-hp IPM motor. The effectiveness of the proposed technique is investigated, both in simulation and experiment, at different operating conditions. It is found that the performance of the FLC-based IPM drive is improved significantly with the proposed TRM technique.
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new online loss minimization based control of an induction motor drive
IEEE Transactions on Power Electronics, 2008Co-Authors: M N Uddin, Sang Woo NamAbstract:This paper presents a new loss-model-based controller for an induction motor drive. Among the many loss minimization algorithms (LMA) for an induction motor, a loss-model-based approach has the advantages of fast response and high accuracy. However, the performance of the loss-model controller (LMC) depends on the accuracy of the modeling of the motor drive and losses. In the development of the loss model, there is always a tradeoff between accuracy and complexity. This paper presents a new LMC to determine an optimum flux level for the efficiency optimization of the vector-controlled induction motor drive. An induction motor (IM) model in d-q coordinates is referenced to the rotor magnetizing current. This transformation results in no leakage inductance on the rotor side, thus the decomposition into d-q components in the steady-state motor model can be utilized in deriving the motor loss model. The suggested LMC is simple, but leakage inductances are not omitted. The complete closed loop vector control of the proposed LMC-based IM drive is successfully implemented in real-time using digital signal Processor Board DS 1104 for a laboratory 1/3 hp motor. The effectiveness of the proposed scheme is demonstrated through simulation and experimental results.
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on line parameter estimation based speed control of pm ac motor drive in flux weakening region
IEEE Industry Applications Society Annual Meeting, 2006Co-Authors: M N Uddin, Md Islam ChyAbstract:This paper presents an online parameter-estimation-based high-speed control of an interior permanent-magnet synchronous motor (IPMSM) drive. The controller designed from standard linear d-q axis motor model with constant parameters will lead to an unsatisfactory prediction of the performance of an IPMSM owing to the magnetic saturation of this motor, particularly, at high-speed conditions. In this paper, an adaptive backstepping-based control technique has been developed for an IPMSM, wherein system parameter variations, as well as field control, will be taken into account at the design stage of the controller. The operating speed limit of the motor is expanded with the proposed parameter-estimation-based field control (PEFC). The complete drive is successfully implemented in real time for a laboratory 1-hp motor using digital signal Processor Board DS1102. The performance of the proposed drive is tested both in simulation and experiment at different operating conditions. A performance comparison of the proposed PEFC with the constant-parameter-based field control is also provided. The robustness of the controller for high-speed applications is evidenced by the results.
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a new and simple structure of fuzzy logic based indirect field oriented control of induction motor drives
Power Electronics Specialists Conference, 2004Co-Authors: T S Radwan, M N Uddin, M.a. RahmanAbstract:This paper presents a novel speed control scheme using a new and simple structure of fuzzy logic controller (FLC) for an induction motor (IM) drive. The proposed FLC is developed to have less computational burden, which makes it suitable for real-time implementation. The parameters of the FLC are tuned by genetic algorithm (GA). The complete drive incorporating the FLC is successfully implemented in real-time using a digital signal Processor Board DS 1102 for a laboratory 1 hp induction motor. The efficacy of the proposed FLC based IM drive is verified by simulation as well as experimental results at various dynamic operating conditions. The proposed FLC is found to be a robust for high performance industrial drive applications.
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development and implementation of a hybrid intelligent controller for interior permanent magnet synchronous motor drives
IEEE Industry Applications Society Annual Meeting, 2002Co-Authors: M N Uddin, M A Abido, M.a. RahmanAbstract:A hybrid neuro-fuzzy scheme for online tuning of a genetic-based proportional-integral (PI) controller for an interior permanent-magnet synchronous motor (IPMSM) drive is presented in this paper. The proposed controller is developed for accurate speed control of the IPMSM drive under various system disturbances. In this work, initially different operating conditions are obtained based on motor dynamics incorporating uncertainties. At each operating condition a genetic algorithm is used to optimize the PI controller parameters in a closed-loop vector control scheme. In the optimization procedure a performance index is developed to reflect the minimum speed deviation, minimum settling time and zero steady-state error. A fuzzy basis function network (FBFN) is utilized for online tuning of the PI controller parameters to ensure optimum drive performance under different disturbances. The proposed FBFN-based PI controller provides a natural framework for combining numerical and linguistic information in a uniform fashion. The proposed controller is successfully implemented in real time using a digital signal Processor Board DS 1102 for a laboratory 1-hp IPMSM. The effectiveness of the proposed controller is verified by simulation as well as experimental results at different dynamic operating conditions. The proposed controller is found to be robust for applications in an IPMSM drive.
Pranjoto Hartono - One of the best experts on this subject based on the ideXlab platform.
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Implementasi Audio Equalizer Digital Grafis dengan Digital Signal Processor Board OMAP-L137
2017Co-Authors: Pranjoto Hartono, Lestariningsih Diana, Suryadinata AdrianAbstract:A digital audio equalizer is implemented using a Digital Signal Processor Board OMAP-L137 with display using a computer monitor with digital control. Traditional audio equalizer with sliding buttons is replaced with a display on a computer screen that is similar to a traditional equalizer-look. The equalizer designed here is a 2/3 octave audio equalizer with left and right audio channel designed in accordance with the standards set forth in ISO 266 1997, IEC 1995 and ISO 61260/1260 3 1973. The standards also mentioned wide band every frequency channels with a bandwidth of bandpass filter with a -3dB at strengthening maximum / minimum +/- 6dB on any frequency channel (left-right independent). The equalizer main component is bandpass filter with a center-predetermined frequency based on standards for the bandwidth of which have been determined in accordance with ISO 266 and so on as mentioned above. Determination is to use the ribbon width of -3dB attenuation on both sides of the bandpass filter, which was also mentioned in the standard. Implementation bandpass filter is to use a Butterworth filter of order 1. The transformation from Butterworth 1st order low pass filter 1 (analog) into a first order bandpass filter (digital) is bilinear Z-transform. Implementation of the digital filter is a signal Processor from Texas Instruments with SDK module OMAP-L137 Processor from Texas Instruments which is able to perform calculations quickly to a digital signal processing system. Every computed bandpass filter will be evaluated fir is amplitude, phase response and bandwidth. The result of the computation for each bandpass filter in general and final implementation will be presented. The performance of OMAP-L137 to handle all the filters without any problems will be presente
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IMPLEMENTASI AUDIO EQUALIZER DIGITAL GRAFIS DENGAN DIGITAL SIGNAL Processor Board OMAP-L137
Program Studi Teknik Elektro, 2016Co-Authors: Pranjoto Hartono, Lestariningsih Diana, Suryadinata AdrianAbstract:Sebuah equalizer audio digital dibuat dengan menggunakan Digital Signal Processor Board OMAP-L137 dan tampilan tombol dirancang secara digital dengan menggunakan komputer. Equalizer audio grafis (audio graphic equalizer) tradisional dengan tombol geser (slider button) akan digantikan dengan sebuah tampilan pada layar komputer yang mirip dengan tampilan tradisional. Equalizer dibuat dengan menggunakan pemisahan kanal audio 2/3 oktaf untuk jalur kiri dan jalur kanan dirancang sesuai dengan standar baku yang dituangkan dalam ISO 266 tahun 1997, IEC 61260/1260 tahun 1995 dan ISO 3 tahun 1973. Pada standar tersebut juga disebutkan lebar pita setiap kanal frekuensi dengan bandwidth -3dB pada bandpass filter dengan penguatan maximum/ minimum +/-6dB pada setiap kanal frekuensi (kiri-kanan independen).Komponen utama equliazer adalah bandpass filter dengan center-frequency yang telah ditentukan berdasarkan standar yang berlaku dengan lebar pita (bandwidth) sebesar yang telah ditentukan sesuai dengan ISO 266 tahun 1997 seperti yang telah disebutkan di atas. Penentuan lebar pita adalah dengan menggunakan attenuasi sebesar -3dB pada kedua sisi dari bandpass filter tersebut yang juga disebutkan dalam standar. Implementasi bandpass filter adalah dengan menggunakan filter Butterworth orde 1 dan pengubah dari lowpass filter Butterworth orde 1 (analog) menjadi bandpass filter orde 1 (digital) menggunakan metode Bilinear Z-transform.Implementasi dari filter digital tersebut adalah sebuah prosesor sinyal dari Texas Instruments dengan modul SDK OMAP-L137 dari Texas Instruments dimana prosesor tersebut mampu melakukan penghitungan secara cepat untuk sebuah sistem pemrosesan sinyal digital. Hasil penghitungan untuk setiap filter dan juga hasil akhir dari implementasi filter ini akan dipaparkan. Kata kunci: digital equalizer 2/3 oktaf, digital signal processing, OMAP-L137, TMS320C674x
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Implementasi Audio Equalizer Digital Grafis Dengan Digital Signal Processor Board Omap-L137
Unika Atama Jaya, 2016Co-Authors: Pranjoto Hartono, Lestariningsih Diana, Suryadinata AdrianAbstract:Sebuah equalizer audio digital dibuat dengan menggunakan Digital Signal Processor Board OMAP-L137 dan tampilan tombol dirancang secara digital dengan menggunakan komputer. Equalizer audio grafis (audio graphic equalizer) tradisional dengan tombol geser (slider button) akan digantikan dengan sebuah tampilan pada layar komputer yang mirip dengan tampilan tradisional. Equalizer dibuat dengan menggunakan pemisahan kanal audio 2/3 oktaf untuk jalur kiri dan jalur kanan dirancang sesuai dengan standar baku yang dituangkan dalam ISO 266 tahun 1997, IEC 61260/1260 tahun 1995 dan ISO 3 tahun 1973. Pada standar tersebut juga disebutkan lebar pita setiap kanal frekuensi dengan bandwidth -3dB pada bandpass filter dengan penguatan maximum/ minimum +/-6dB pada setiap kanal frekuensi (kiri-kanan independen). Komponen utama equliazer adalah bandpass filter dengan center-frequency yang telah ditentukan berdasarkan standar yang berlaku dengan lebar pita (bandwidth) sebesar yang telah ditentukan sesuai dengan ISO 266 tahun 1997 seperti yang telah disebutkan di atas. Penentuan lebar pita adalah dengan menggunakan attenuasi sebesar -3dB pada kedua sisi dari bandpass filter tersebut yang juga disebutkan dalam standar. Implementasi bandpass filter adalah dengan menggunakan filter Butterworth orde 1 dan pengubah dari lowpass filter Butterworth orde 1 (analog) menjadi bandpass filter orde 1 (digital) menggunakan metode Bilinear Z-transform. Implementasi dari filter digital tersebut adalah sebuah prosesor sinyal dari Texas Instruments dengan modul SDK OMAP-L137 dari Texas Instruments dimana prosesor tersebut mampu melakukan penghitungan secara cepat untuk sebuah sistem pemrosesan sinyal digital. Hasil penghitungan untuk setiap filter dan juga hasil akhir dari implementasi filter ini akan dipaparkan
Atlas Collaboration - One of the best experts on this subject based on the ideXlab platform.
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ATLAS Level-1 Endcap Muon Trigger from Run-2 to Run-3
2020Co-Authors: Nobe Takuya, Atlas CollaborationAbstract:The LHC is expected to increase its center-of-mass energy to 14 TeV and to keep longer time with an instantaneous luminosity of about 2.0×10^34 cm^-2s^-1 for Run-3 scheduled from 2021 to 2024. In order to cope with the high event rate, upgrades of the ATLAS trigger system are required. The level-1 Endcap Muon trigger system identifies muons with high transverse momentum by combining data from a fast muon trigger detector, Thin-Gap Chamber. In the ongoing upgrade in this year, new detectors called the New-Small-Wheel (NSW) and RPC-BIS78, will be installed in the inner station region for the endcap muon trigger. Finer track information from the NSW and RPC-BIS78 can be used as part of the muon trigger logic to enhance performance significantly. In order to handle data from both TGC and NSW, some new electronics have been developed, including the trigger Processor Board known as Sector Logic (SL). The SL Board has a modern FPGA to make use of Multi-Gigabit transceiver technology, which will be used to receive data from the NSW. Increasing of the FPGA resource also makes to improve the momentum resolution and additional information, such as charge identification. This presentation describes the aforementioned upgrades of the level-1 Endcap Muon trigger system. Particular emphasis will be placed on the new algorithm in Sector Logic and the current status of installation and commissioning. The expected trigger performance by the new algorithm will also be discussed
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ATLAS Level-1 Endcap Muon Trigger for Run-3
2020Co-Authors: Maeda Jumpei, Atlas CollaborationAbstract:The LHC is expected to increase its centre-of-mass energy to 14 TeV and to keep longer time with an instantaneous luminosity of about 2.0\times10^{34} cm^{-2}s^{-1} for Run-3 scheduled from 2021 to 2024. In order to cope with the high event rate, upgrades of the ATLAS trigger system are required. The level-1 endcap muon trigger system identifies muons with high transverse momentum by combining data from a fast muon trigger detector, Thin-Gap Chamber. In the ongoing upgrade in this year, new detectors called the New-Small-Wheel (NSW) and RPC-BIS78, will be installed in the inner station region for the endcap muon trigger. Finer track information from the NSW and RPC-BIS78 can be used as part of the muon trigger logic to enhance performance significantly. In order to handle data from both TGC and NSW, some new electronics have been developed, including the trigger Processor Board known as Sector Logic (SL). The SL Board has a modern FPGA to make use of Multi-Gigabit transceiver technology, which will be used to receive data from the NSW. The readout system for trigger data has also been re-designed, with the data transfer implemented with TCP/IP instead of a dedicated ASIC. This makes it possible to minimise the use of custom readout electronics and instead use some commercial PCs and network switches to collect, format and send the data. This presentation describes the aforementioned upgrades of the level-1 endcap muon trigger system. Particular emphasis will be placed on the new algorithm in Sector Logic and the current status of installation and commissioning. The expected trigger performance by the new algorithm will also be discussed
Mino Yuya - One of the best experts on this subject based on the ideXlab platform.
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ATLAS hardware-based Endcap Muon Trigger for future upgrades
2020Co-Authors: Mino YuyaAbstract:The LHC is expected to increase its center-of-mass energy from 13 TeV to 14 TeV for Run-3 scheduled from 2022 to 2024. After Run-3, upgrades for the High-Luminosity-LHC (HL-LHC) program is planned and the operation will start from 2027, increasing the instantaneous luminosity to 5.0 -- 7.5 times its nominal luminosity. Continuous upgrades of the ATLAS trigger system is planned to cope with the high event rate and keep the physics acceptance. During the Phase-1 Upgrade for Run-3, new detectors will be installed to improve the trigger performance. New trigger logic, combining information from detectors outside the magnetic field and new detectors installed inside the magnetic field, is introduced from Run-3 to reduce the trigger rate. In order to handle data from various detectors, a new trigger Processor Board has been developed and the design is presented. During the Phase-2 Upgrade for HL-LHC, the trigger and readout systems of the hardware-based trigger are planned to be upgraded. Full-granular information will be transferred to the trigger Processor Board which enables hardware-based track reconstruction to reconstruct off-line like tracks. To handle the full-granular information and perform the hardware-based track reconstruction, the trigger Processor Board will implement an FPGA with hundred of pairs of transceivers and huge memory resources. Expected trigger performance for the hardware-based endcap muon trigger in Run-3 and HL-LHC will also be presented
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ATLAS hardware-based Endcap Muon Trigger for future upgrades
2020Co-Authors: Mino YuyaAbstract:The LHC is expected to increase its center-of-mass energy to 14 TeV with an instantaneous luminosity to $2×10^{34} \mathrm{cm^{-2}s^{-1}}$ for Run 3 scheduled from 2021 to 2023. The High-Luminosity-LHC (HL-LHC) program is then planned to start the operation in 2026 with an instantaneous luminosity of $7.5×10^{34} \mathrm{cm^{-2}s^{-1}}$. In order to cope with the high event rate, continuous upgrades of the ATLAS trigger system is mandatory. The hardware-based Endcap Muon trigger system identifies muons with high transverse momentum by combining data from a fast muon trigger detector, TGC. In the ongoing upgrade for Run 3, new detectors will be installed in the inner station region for the endcap muon trigger. In order to handle data from various detectors, some new electronics have been developed, including the trigger Processor Board known as Sector Logic. Finer track information from the new detectors can be used as part of the muon trigger logic to enhance performance significantly. For HL-LHC, the new hardware muon trigger is required to reconstruct muon candidates with an improved momentum resolution to suppress the trigger rate with keeping the efficiency. The track reconstruction using full-granular information enables to form more offline-like tracks, by Virtex UltraScale+ FPGA with about hundred pairs of transceivers, and with huge memory resources for a pattern matching algorithm. This presentation describes the aforementioned upgrades of the hardware-based Endcap Muon trigger system. Particular emphasis will be placed on the new electronics design and the firmware. The expected trigger performance will also be discussed